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ST
Sitronix
1. INTRODUCTION
ST7626
65K Color Dot Matrix LCD Controller/Driver
The ST7626 is a driver & controller LSI for 65K color graphic dot-matrix liquid crystal display systems. It generates 294 Segment and 68 Common driver circuits. This chip is connected directly to a microprocessor, accepts Serial Peripheral Interface (SPI) or 8-bit/16-bit parallel display data and stores in an on-chip display data RAM. It performs display data RAM read/write operation with no external operating clock to minimize power consumption. In addition, because it contains power supply circuits necessary to drive liquid crystal, it is possible to make a display system with the fewest components.
2. FEATURES
Driver Output Circuits
294 Segment Outputs / 68 Common Outputs
On-chip Voltage Converter (x2, x3, x4, x5) with internal booster capacitors. Extremely Few Outsider Compoment. (Minimum required outsider compoments: One Capacitor). On-chip Voltage Regulator (Temperature gradient = -0.065%/C) On-chip Electronic Contrast Control Function (406 steps) Voltage Follower (LCD bias: 1/5 to 1/12)
Applicable Duty Ratios
Various Partial Display Partial Window Moving & Data Scrolling
Gray-Scale Display
4FRC & 31 PWM function circuit to display 64 gray-scale display.
Operating Voltage Range
Supply Digital Voltage (VDD, VDD1): 1.8 to 3.3V Supply Analog Voltage (VDD2, VDD3, VDD4, VDD5): 2.4 to 3.3V LCD Driving Voltage (VOP = V0 - VSS): 3.76V to 18V The suggested value of V0 is under 11 V with bias =1/9.
On-chip Display Data RAM
Capacity: 98 x 68 x 16 =106,624 bits 4K colors (RGB)=(444) mode 65K colors (RGB)=(565) mode Truncated 262K colors (RGB)=(666) mode Truncated 16M colors (RGB)=(888) mode
LCD Driving Voltage (EEPROM)
Contrast Adjustment Value is stored in the Built-In EEPROM for better display quility.
Microprocessor Interface
8/16-bit parallel bi-directional interface with 6800-series or 8080-series 4-line serial interface (4-line-SIF) 3-line serial interface (3-line-SIF)
LCM Performance Adjustment (EEPROM)
Adjustment Value for best Display Performance is stored in the Built-In EEPROM.
On-chip Low Power Analog Circuit
On-chip Oscillator Circuit
Package Type
Application for COG
ST7626
Ver 1.5
6800 , 8080 ,4-Line , 3-Line interface
1/94 2007/01/20
ST7626
3. ST7626 Pad Arrangement (COG)
Chip Size : 9,717 um x 1,352.7 um Bump Pitch :
PAD NO.1~328, 412~445 : 31 um (COM/SEG) PAD NO.329~341, 342~411, : 110 um (I/O) PAD NO.341~342 : 114.7 um (I/O)
Bump Size :
PAD NO.1~328, 412~445 : 16 um(x) X 118 um(y) PAD NO.329~411 : 95 um(x) X 50 um(y)
Bump Height : 15 um Chip Thickness : 400 um
x
y
20 um
20 um
52 um 52 um
(x , y) = (4762.7 um,580.35 um)
20 um
(x , y) = (-4778.7 um,596.35 um)
52 um 20 um 52 um
Ver 1.5
2/94
2007/01/20
ST7626
4. Pad Center Coordinates
PIN Name PAD No. CSEL=0 CSEL=1 001 002 003 004 005 006 007 008 009 010 011 012 013 014 015 016 017 018 019 020 021 022 023 024 025 026 027 028 029 030 031 032 033
Ver 1.5
X 4541.5 4510.5 4479.5 4448.5 4417.5 4386.5 4355.5 4324.5 4293.5 4262.5 4231.5 4200.5 4169.5 4138.5 4107.5 4076.5 4045.5 4014.5 3983.5 3952.5 3921.5 3890.5 3859.5 3828.5 3797.5 3766.5 3735.5 3704.5 3673.5 3642.5 3611.5 3580.5 3549.5
Y 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35
PIN Name PAD No. CSEL=0 CSEL=1 034 035 036 037 038 039 040 041 042 043 044 045 046 047 048 049 050 051 052 053 054 055 056 057 058 059 060 061 062 063 064 065 066
3/94
X 3518.5 3487.5 3456.5 3425.5 3394.5 3363.5 3332.5 3301.5 3270.5 3239.5 3208.5 3177.5 3146.5 3115.5 3084.5 3053.5 3022.5 2991.5 2960.5 2929.5 2898.5 2867.5 2836.5 2805.5 2774.5 2743.5 2712.5 2681.5 2650.5 2619.5 2588.5 2557.5 2526.5
Y 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35
SEG[293] SEG[292] SEG[291] SEG[290] SEG[289] SEG[288] SEG[287] SEG[286] SEG[285] SEG[284] SEG[283] SEG[282] SEG[281] SEG[280] SEG[279] SEG[278] SEG[277] SEG[276] SEG[275] SEG[274] SEG[273] SEG[272] SEG[271] SEG[270] SEG[269] SEG[268] SEG[267] SEG[266] SEG[265] SEG[264] SEG[263] SEG[262] SEG[261]
SEG[260] SEG[259] SEG[258] SEG[257] SEG[256] SEG[255] SEG[254] SEG[253] SEG[252] SEG[251] SEG[250] SEG[249] SEG[248] SEG[247] SEG[246] SEG[245] SEG[244] SEG[243] SEG[242] SEG[241] SEG[240] SEG[239] SEG[238] SEG[237] SEG[236] SEG[235] SEG[234] SEG[233] SEG[232] SEG[231] SEG[230] SEG[229] SEG[228]
2007/01/20
ST7626
PIN Name PAD No. CSEL=0 CSEL=1 067 068 069 070 071 072 073 074 075 076 077 078 079 080 081 082 083 084 085 086 087 088 089 090 091 092 093 094 095 096 097 098 099 100 101
Ver 1.5 X Y
PIN Name PAD No. CSEL=0 CSEL=1 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136
4/94
X 1410.5 1379.5 1348.5 1317.5 1286.5 1255.5 1224.5 1193.5 1162.5 1131.5 1100.5 1069.5 1038.5 1007.5 976.5 945.5 914.5 883.5 852.5 821.5 790.5 759.5 728.5 697.5 666.5 635.5 604.5 573.5 542.5 511.5 480.5 449.5 418.5 387.5 356.5
Y 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35
SEG[227] SEG[226] SEG[225] SEG[224] SEG[223] SEG[222] SEG[221] SEG[220] SEG[219] SEG[218] SEG[217] SEG[216] SEG[215] SEG[214] SEG[213] SEG[212] SEG[211] SEG[210] SEG[209] SEG[208] SEG[207] SEG[206] SEG[205] SEG[204] SEG[203] SEG[202] SEG[201] SEG[200] SEG[199] SEG[198] SEG[197] SEG[196] SEG[195] SEG[194] SEG[193]
2495.5 2464.5 2433.5 2402.5 2371.5 2340.5 2309.5 2278.5 2247.5 2216.5 2185.5 2154.5 2123.5 2092.5 2061.5 2030.5 1999.5 1968.5 1937.5 1906.5 1875.5 1844.5 1813.5 1782.5 1751.5 1720.5 1689.5 1658.5 1627.5 1596.5 1565.5 1534.5 1503.5 1472.5 1441.5
545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35
SEG[192] SEG[191] SEG[190] SEG[189] SEG[188] SEG[187] SEG[186] SEG[185] SEG[184] SEG[183] SEG[182] SEG[181] SEG[180] SEG[179] SEG[178] SEG[177] SEG[176] SEG[175] SEG[174] SEG[173] SEG[172] SEG[171] SEG[170] SEG[169] SEG[168] SEG[167] SEG[166] SEG[165] SEG[164] SEG[163] SEG[162] SEG[161] SEG[160] SEG[159] SEG[158]
2007/01/20
ST7626
PIN Name PAD No. CSEL=0 CSEL=1 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171
Ver 1.5 X Y
PIN Name PAD No. CSEL=0 CSEL=1 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206
5/94
X -759.5 -790.5 -821.5 -852.5 -883.5 -914.5 -945.5 -976.5
Y 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35
SEG[157] SEG[156] SEG[155] SEG[154] SEG[153] SEG[152] SEG[151] SEG[150] SEG[149] SEG[148] SEG[147] SEG[146] SEG[145] SEG[144] SEG[143] SEG[142] SEG[141] SEG[140] SEG[139] SEG[138] SEG[137] SEG[136] SEG[135] SEG[134] SEG[133] SEG[132] SEG[131] SEG[130] SEG[129] SEG[128] SEG[127] SEG[126] SEG[125] SEG[124] SEG[123]
325.5 294.5 263.5 232.5 201.5 170.5 139.5 108.5 77.5 46.5 15.5 -15.5 -46.5 -77.5 -108.5 -139.5 -170.5 -201.5 -232.5 -263.5 -294.5 -325.5 -356.5 -387.5 -418.5 -449.5 -480.5 -511.5 -542.5 -573.5 -604.5 -635.5 -666.5 -697.5 -728.5
545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35 545.35
SEG[122] SEG[121] SEG[120] SEG[119] SEG[118] SEG[117] SEG[116] SEG[115] SEG[114] SEG[113] SEG[112] SEG[111] SEG[110] SEG[109] SEG[108] SEG[107] SEG[106] SEG[105] SEG[104] SEG[103] SEG[102] SEG[101] SEG[100] SEG[99] SEG[98] SEG[97] SEG[96] SEG[95] SEG[94] SEG[93] SEG[92] SEG[91] SEG[90] SEG[89] SEG[88]
-1007.5 545.35 -1038.5 545.35 -1069.5 545.35 -1100.5 545.35 -1131.5 545.35 -1162.5 545.35 -1193.5 545.35 -1224.5 545.35 -1255.5 545.35 -1286.5 545.35 -1317.5 545.35 -1348.5 545.35 -1379.5 545.35 -1410.5 545.35 -1441.5 545.35 -1472.5 545.35 -1503.5 545.35 -1534.5 545.35 -1565.5 545.35 -1596.5 545.35 -1627.5 545.35 -1658.5 545.35 -1689.5 545.35 -1720.5 545.35 -1751.5 545.35 -1782.5 545.35 -1813.5 545.35
2007/01/20
ST7626
PIN Name PAD No. CSEL=0 CSEL=1 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241
Ver 1.5 X Y
PIN Name PAD No. CSEL=0 CSEL=1 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276
6/94
X
Y
SEG[87] SEG[86] SEG[85] SEG[84] SEG[83] SEG[82] SEG[81] SEG[80] SEG[79] SEG[78] SEG[77] SEG[76] SEG[75] SEG[74] SEG[73] SEG[72] SEG[71] SEG[70] SEG[69] SEG[68] SEG[67] SEG[66] SEG[65] SEG[64] SEG[63] SEG[62] SEG[61] SEG[60] SEG[59] SEG[58] SEG[57] SEG[56] SEG[55] SEG[54] SEG[53]
-1844.5 545.35 -1875.5 545.35 -1906.5 545.35 -1937.5 545.35 -1968.5 545.35 -1999.5 545.35 -2030.5 545.35 -2061.5 545.35 -2092.5 545.35 -2123.5 545.35 -2154.5 545.35 -2185.5 545.35 -2216.5 545.35 -2247.5 545.35 -2278.5 545.35 -2309.5 545.35 -2340.5 545.35 -2371.5 545.35 -2402.5 545.35 -2433.5 545.35 -2464.5 545.35 -2495.5 545.35 -2526.5 545.35 -2557.5 545.35 -2588.5 545.35 -2619.5 545.35 -2650.5 545.35 -2681.5 545.35 -2712.5 545.35 -2743.5 545.35 -2774.5 545.35 -2805.5 545.35 -2836.5 545.35 -2867.5 545.35 -2898.5 545.35
SEG[52] SEG[51] SEG[50] SEG[49] SEG[48] SEG[47] SEG[46] SEG[45] SEG[44] SEG[43] SEG[42] SEG[41] SEG[40] SEG[39] SEG[38] SEG[37] SEG[36] SEG[35] SEG[34] SEG[33] SEG[32] SEG[31] SEG[30] SEG[29] SEG[28] SEG[27] SEG[26] SEG[25] SEG[24] SEG[23] SEG[22] SEG[21] SEG[20] SEG[19] SEG[18]
-2929.5 545.35 -2960.5 545.35 -2991.5 545.35 -3022.5 545.35 -3053.5 545.35 -3084.5 545.35 -3115.5 545.35 -3146.5 545.35 -3177.5 545.35 -3208.5 545.35 -3239.5 545.35 -3270.5 545.35 -3301.5 545.35 -3332.5 545.35 -3363.5 545.35 -3394.5 545.35 -3425.5 545.35 -3456.5 545.35 -3487.5 545.35 -3518.5 545.35 -3549.5 545.35 -3580.5 545.35 -3611.5 545.35 -3642.5 545.35 -3673.5 545.35 -3704.5 545.35 -3735.5 545.35 -3766.5 545.35 -3797.5 545.35 -3828.5 545.35 -3859.5 545.35 -3890.5 545.35 -3921.5 545.35 -3952.5 545.35 -3983.5 545.35
2007/01/20
ST7626
PIN Name PAD No. CSEL=0 CSEL=1 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 SEG[17] SEG[16] SEG[15] SEG[14] SEG[13] SEG[12] SEG[11] SEG[10] SEG[9] SEG[8] SEG[7] SEG[6] SEG[5] SEG[4] SEG[3] SEG[2] SEG[1] SEG[0] X Y PIN Name PAD No. CSEL=0 CSEL=1 X Y -57.35 -88.35
-4014.5 545.35 -4045.5 545.35 -4076.5 545.35 -4107.5 545.35 -4138.5 545.35 -4169.5 545.35 -4200.5 545.35 -4231.5 545.35 -4262.5 545.35 -4293.5 545.35 -4324.5 545.35 -4355.5 545.35 -4386.5 545.35 -4417.5 545.35 -4448.5 545.35 -4479.5 545.35 -4510.5 545.35 -4541.5 545.35
312 COM[51] COM[33] -4727.7 313 COM[52] COM[31] -4727.7
314 COM[53] COM[29] -4727.7 -119.35 315 COM[54] COM[27] -4727.7 -150.35 316 COM[55] COM[25] -4727.7 -181.35 317 COM[56] COM[23] -4727.7 -212.35 318 COM[57] COM[21] -4727.7 -243.35 319 COM[58] COM[19] -4727.7 -274.35 320 COM[59] COM[17] -4727.7 -305.35 321 COM[60] COM[15] -4727.7 -336.35 322 COM[61] COM[13] -4727.7 -367.35 323 COM[62] COM[11] -4727.7 -398.35 324 COM[63] COM[9] 325 COM[64] COM[7] 326 COM[65] COM[5] 327 COM[66] COM[3] 328 COM[67] COM[1] 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346
7/94
-4727.7 -429.35 -4727.7 -460.35 -4727.7 -491.35 -4727.7 -522.35 -4727.7 -553.35 -4510.0 -575.35 -4400.0 -575.35 -4290.0 -575.35 -4180.0 -575.35 -4070.0 -575.35 -3960.0 -575.35 -3850.0 -575.35 -3740.0 -575.35 -3630.0 -575.35 -3520.0 -575.35 -3410.0 -575.35 -3300.0 -575.35 -3190.0 -575.35 -3075.3 -575.35 -2965.3 -575.35 -2855.3 -575.35 -2745.3 -575.35 -2635.3 -575.35
2007/01/20
V0IN V0IN V0IN V0IN V0IN V0IN V0OUT V0OUT V1 V2 V3 V4 VREF CL CLS VSS VDD A0
295 COM[34] COM[67] -4727.7 469.65 296 COM[35] COM[65] -4727.7 438.65 297 COM[36] COM[63] -4727.7 407.65 298 COM[37] COM[61] -4727.7 376.65 299 COM[38] COM[59] -4727.7 345.65 300 COM[39] COM[57] -4727.7 314.65 301 COM[40] COM[55] -4727.7 283.65 302 COM[41] COM[53] -4727.7 252.65 303 COM[42] COM[51] -4727.7 221.65 304 COM[43] COM[49] -4727.7 190.65 305 COM[44] COM[47] -4727.7 159.65 306 COM[45] COM[45] -4727.7 128.65 307 COM[46] COM[43] -4727.7 308 COM[47] COM[41] -4727.7 309 COM[48] COM[39] -4727.7 310 COM[49] COM[37] -4727.7 311 COM[50] COM[35] -4727.7
Ver 1.5
97.65 66.65 35.65 4.65 -26.35
ST7626
PIN Name PAD No. CSEL=0 CSEL=1 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381
Ver 1.5
X
Y
PIN Name PAD No. CSEL=0 CSEL=1 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416
8/94
X
Y
RW_WR D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 VSS VDD E_RD RST CSEL IF1 IF2 IF3 VSS VDD SI SCL /CS VDD VDD VDD1 VSS1 VSS
-2525.3 -575.35 -2415.3 -575.35 -2305.3 -575.35 -2195.3 -575.35 -2085.3 -575.35 -1975.3 -575.35 -1865.3 -575.35 -1755.3 -575.35 -1645.3 -575.35 -1535.3 -575.35 -1425.3 -575.35 -1315.3 -575.35 -1205.3 -575.35 -1095.3 -575.35 -985.3 -875.3 -765.3 -655.3 -545.3 -435.3 -325.3 -215.3 -105.3 4.7 114.7 224.7 334.7 444.7 554.7 664.7 774.7 884.7 994.7 -575.35 -575.35 -575.35 -575.35 -575.35 -575.35 -575.35 -575.35 -575.35 -575.35 -575.35 -575.35 -575.35 -575.35 -575.35 -575.35 -575.35 -575.35 -575.35
VSS VSS VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS2 VSS4 VDD4 VDD3 VDD2 VDD2 VDD2 VDD2 VDD2 VDD5 VDD5 VDD5 TCAP VLCDIN VLCDIN VLCDIN VLCDIN VLCDIN VLCDIN VLCDOUT VLCDOUT COM[0] COM[1] COM[2] COM[3] COM[4]
1324.7 -575.35 1434.7 -575.35 1544.7 -575.35 1654.7 -575.35 1764.7 -575.35 1874.7 -575.35 1984.7 -575.35 2094.7 -575.35 2204.7 -575.35 2314.7 -575.35 2424.7 -575.35 2534.7 -575.35 2644.7 -575.35 2754.7 -575.35 2864.7 -575.35 2974.7 -575.35 3084.7 -575.35 3194.7 -575.35 3304.7 -575.35 3414.7 -575.35 3524.7 -575.35 3634.7 -575.35 3744.7 -575.35 3854.7 -575.35 3964.7 -575.35 4074.7 -575.35 4184.7 -575.35 4294.7 -575.35 4404.7 -575.35 4514.7 -575.35
COM[0] 4727.7 -553.35 COM[2] 4727.7 -522.35 COM[4] 4727.7 -491.35 COM[6] 4727.7 -460.35 COM[8] 4727.7 -429.35
2007/01/20
1104.7 -575.35 1214.7 -575.35
ST7626
PIN Name PAD No. CSEL=0 CSEL=1 417 418 419 420 421 X Y
COM[5] COM[10] 4727.7 -398.35 COM[6] COM[12] 4727.7 -367.35 COM[7] COM[14] 4727.7 -336.35 COM[8] COM[16] 4727.7 -305.35 COM[9] COM[18] 4727.7 -274.35
422 COM[10] COM[20] 4727.7 -243.35 423 COM[11] COM[22] 4727.7 -212.35 424 COM[12] COM[24] 4727.7 -181.35 425 COM[13] COM[26] 4727.7 -150.35 426 COM[14] COM[28] 4727.7 -119.35 427 COM[15] COM[30] 4727.7 428 COM[16] COM[32] 4727.7 429 COM[17] COM[34] 4727.7 430 COM[18] COM[36] 4727.7 431 COM[19] COM[38] 4727.7 432 COM[20] COM[40] 4727.7 433 COM[21] COM[42] 4727.7 434 COM[22] COM[44] 4727.7 435 COM[23] COM[46] 4727.7 436 COM[24] COM[48] 4727.7 437 COM[25] COM[50] 4727.7 438 COM[26] COM[52] 4727.7 439 COM[27] COM[54] 4727.7 440 COM[28] COM[56] 4727.7 441 COM[29] COM[58] 4727.7 442 COM[30] COM[60] 4727.7 443 COM[31] COM[62] 4727.7 444 COM[32] COM[64] 4727.7 445 COM[33] COM[66] 4727.7 -88.35 -57.35 -26.35 4.65 35.65 66.65 97.65 128.65 159.65 190.65 221.65 252.65 283.65 314.65 345.65 376.65 407.65 438.65 469.65
Ver 1.5
9/94
2007/01/20
ST7626
5. BLOCK DIAGRAM
SEG0 TO SEG293
COM0 TO COM67
VDD1 VDD
V0IN V1 V2 V3 V4 VSS SEGMENT DRIVERS COMMON DRIVERS
CSEL
DATA LATCHES V/F Circuit
V0OUT
V/R Circuit
FRC/PWM FUNCTION CIRCUIT
COMMON OUTPUT CONTROLLER CIRCUIT RESET OSCILLATOR
CL CLS
DISPLAY DATA RAM (DDRAM) [98 X 68 X 16]
VLCDIN VLCDOUT
V/C Circuit ADDRESS COUNTER
TIMING GENERATOR DISPLAY ADDRESS COUNTER EEPROM
VDD2 VDD3 VDD4 VDD5 VSS2 VSS4 VSS VSS1
DATA REGISTER BUS HOLDER
INSTRUCTION REGISTER INSTRUCTION DECODER
MPU INTERFACE(PARALLEL & SERIAL)
SI SCL E_RD RW_WR
TCAP D0 to D15
IF3 IF2 IF1
A0 /CS /RST
Ver 1.5
10/94
2007/01/20
ST7626
6. PIN DESCRIPTION
6.1 POWER SUPPLY
Name
VDD VDD1 VDD2 VDD3 VDD4 VDD5 VSS VSS1 VSS2 VSS4
I/O
Supply Supply Supply Supply Supply Supply Supply Supply Supply Supply Power supply for logic circuit Power supply for OSC circuit Power supply for Booster Circuit Power supply for LCD. Power supply for LCD. Power supply for LCD.
Description
Ground for logic circuit. Ground system should be connected together. Ground for OSC circuit. Ground system should be connected together. Ground for Booster Circuit. Ground system should be connected together. Ground for LCD. Ground system should be connected together.
6.2 LCD Power Supply Pins
VLCDOUT VLCDIN O I If the internal voltage generator is used, the VLCDIN & VLCDOUT must be connected together. If an external supply is used, this pin must be left open. An external LCD supply voltage can be supplied using the VLCDIN pin. In this case, VLCDOUT has to be left open, and the internal voltage generator has to be programmed to zero. (SET register VC=0) LCD driver supply voltages V0in & V0out should be connected together. V0IN V0OUT V1 V2 V3 V4 I/O Voltages should have the following relationship; V0 ( V0in ) U V1 U V2 U V3 U V4 U VSS.
When the internal power circuit is active, these voltages are generated as following table according to the state of LCD bias. LCD bias 1/N bias NOTE: N = 5 to 12 V1 (N-1) / N x V0 V2 (N-2) / N x V0 V3 (2/N) x V0 V4 (1/N) x V0
6.3 SYSTEM CONTROL
Name
CLS
I/O
I
Description
When using internal clock oscillator, connect CLS to VDD. When using external clock oscillator, connect CLS to VSS. When using internal clock oscillator, it's oscillator output. When using external clock oscillator, it's clock input. Select Common output direction.
CL
I/O
CSEL
I
CSEL="L", COM0~COM33 is in one side, COM34~COM67 is in the opposite side. CSEL="H", COM2n(even number) is in the one side, COM2n+1 (odd number) is in the opposite side.
TCAP VREF
I/O O
Test pin. Left it opens. Reference voltage output for monitor only. Left it opened. Do NOT connect this PAD.
Ver 1.5
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2007/01/20
ST7626
6.4 MICROPROCESSOR INTERFACE
Name
RST
I/O
I
Description
Reset input pin. When RESETB is "L", initialization is executed. Parallel / Serial data input select input IF1 H IF2 H H L H L L IF3 H L L H H L MPU interface type 80 series 16-bit parallel 80 series 8-bit parallel 68 series 16-bit parallel 68 series 8-bit parallel 9-bit serial (3 line) 8-bit serial (4 line)
IF[3:1]
I
H H L L L Chip select input pins
/CS
I
Data / Instruction I/O is enabled only when /CS is "L". When chip select is non-active, D0 to D15 become high impedance. Register select input pin
A0
I
A0 = "H": D0 to D15 or SI are display data A0 = "L": D0 to D15 or SI are control data In 3-line interface not let it floating, connect it to "H" level. Read / Write execution control pin MPU type RW_WR Description Read / Write control input pin 6800-series RW RW = "H" : read RW = "L" : write Write enable clock input pin 8080-series /WR The data on D0 to D15 are latched at the rising edge of the /WR signal. When in the serial interface, connect it to "H" level. Read / Write execution control pin MPU Type E_RD Description Read / Write control input pin RW = "H": When E is "H", D0 to D15 are in an output
RW_WR
I
E_RD
I
6800-series
E
status. RW = "L": The data on D0 to D15 are latched at the falling edge of the E signal.
8080-series
/RD
Read enable clock input pin When /RD is "L", D0 to D15 are in an output status.
When in the serial interface, connect it to "H" level .Signals Explaination ChartG see page 17
Ver 1.5
12/94
2007/01/20
ST7626
They connect to the standard 8-bit or 16 bit MPU bus via the 8/16 -bit bi-directional bus. When the following interface is selected and the /CS pin is high, the following pins become high D15 to D0 I/O impedance. 1. 2. In 8-bit parallel: D15-D8 pins are in the state of high impedance should connect to "H" level. In Serial interface: D15-D0 pins are in the state of high impedance should connect to "H" level. SI I This pin is used to input serial data when the serial interface is selected.(3 line and 4 line) When not use connect it to "H" level. This pin is used to input serial clock when the serial interface is selected. SCL I The data is converted in the rising edge. (3 line and 4 line) When not use connect it to "H" level.
NOTE: Microprocessor interfece pins should not be floating in any operation mode.
6.5 LCD DRIVER OUTPUTS
Name I/O LCD segment driver outputs The display data and the M signal control the output voltage of segment driver. Display data SEG0 to SEG293 O H H L L Sleep-In mode M (Internal) H L H L Segment driver output voltage Normal display V0 VSS V2 V3 VSS Reverse display V2 V3 V0 VSS VSS Description
LCD common driver outputs The internal scanning data and M signal control the output voltage of common driver.
Scan data COM0 to COM67 O H H L L
M (Internal) H L H L
Common driver output voltage VSS V0 V1 V4 VSS
Sleep-In mode
Ver 1.5
13/94
2007/01/20
ST7626
ST7626 I/O PIN ITO Resister Limitation Pin Name TCAP, CL IF[3:1],CLS,CSEL VDD, VDD1~VDD5, VSS,VSS1,VSS2,VSS4,VLCDIN, VLCDOUT V0IN, V0OUT, V1, V2, V3, V4 A0, E_RD, RW_WR, /CS, D0 ...D15, SCL, SI RST NOTE: Make sure that the ITO resistance of COM0 ~ COM67 is equal, and so is it of SEG0 ~ SEG293. Vref sould not connect to external. Therefore, no ITO resistance value listed. ITO Resister Floating No Limitation <100 <100 <1K <10K
Ver 1.5
14/94
2007/01/20
ST7626
7. FUNCTIONAL DESCRIPTION
7.1 MICROPROCESSOR INTERFACE
Chip Select Input
/CS pin is for chip selection. The ST7626 can function with an MPU when /CS is "L". In case of serial interface, the internal shift register and the counter are reset.
7.1.1 Selecting Parallel / Serial Interface
ST7626 has six types of interface with an MPU, which are two serial and four parallel interfaces. This parallel or serial interface is determined by IF pin as shown in table 7.1.1.
Table 7.1.1 Parallel / Serial Interface Mode
I/F Mode IF1 IF2 IF3 H H H H H L H L L L H H L L L L L H I/F Description 80 serial 16-bit parallel 80 serial 8-bit parallel 68 serial 16-bit parallel 68 serial 8-bit parallel 8-bit SPI mode (4 line) 9-bit SPI mode (3 line) /CS /CS /CS /CS /CS /CS /CS A0 A0 A0 A0 A0 A0 -E_RD /RD /RD E E --Pin Assignment RW_WR D15 to D8 /WR D15 ~ D8 /WR -R/W D15 ~ D8 R/W -----D7 to D0 D7 ~ D0 D7 ~ D0 D7 ~ D0 D7 ~ D0 --SI ----SI SI SCL ----SCL SCL
NOTE: When these pins are set to any other combination, A0, E_RD and RW_WR inputs are disabled and D0 to D15 are to be high impedance.
7.1.2 8-bit or 16-bit Parallel Interface
The ST7626 identifies the type of the data bus signals according to the combination of A0, /RD (E) and /WR (W/R) signals, as shown in table 7.1.2.
Table 7.1.2 Parallel Data Transfer
Common A0 H H L L 6800-series R/W H L H L E H H H H /RD L H L H 8080-series /WR H L H L Description Display data read out Display data write Register status read Writes to internal register (instruction)
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ST7626
Figure 7.1.2 Parallel Data Transfer Example Chart
Relation between Data Bus and Gradation Data ST7626 offers 4096 color display, 65K color display, truncated 262K color display, and truncated 16M color display. When using 4096, 65K, 262K, and 16M color display; you can specify color for each of R, G, B using the palette function. Use the command for switching between these modes.
(1) 4096-color display (1-1) Type A 4096 color display 1. 8-bit mode D7, D6, D5, D4, D3, D2, D1, D0: RRRRGGGG D7, D6, D5, D4, D3, D2, D1, D0: BBBBRRRR D7, D6, D5, D4, D3, D2, D1, D0: GGGGBBBB 1st write 2nd write 3rd write
2 pixels of data are read after the third write operation as shown, and it is written in the display RAM.
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ST7626
2. 16-bit mode D15, D14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0: RRRRGGGGBBBBXXXX Data is acquired through signal write operation and then written to the display RAM. "XXXX" are dummy bits, and they are ignored for display.
(1-2) Type B 4096 color display 1. 8-bit mode D7, D6, D5, D4, D3, D2, D1, D0: XXXXRRRR D7, D6, D5, D4, D3, D2, D1, D0: GGGGBBBB 1st write 2nd write
A single pixel of data is read after the second write operation as shown, and it is written in the display RAM.
2. 16-bit mode D15, D14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0: XXXXRRRRGGGGBBBB A single pixel of data is read and written in the display RAM in a single write operation. "XXXX" are dummy bits, and they are ignored for display.
(2) 65K color input mode 1. 8-bit mode D7, D6, D5, D4, D3, D2, D1, D0: RRRRRGGG D7, D6, D5, D4, D3, D2, D1, D0: GGGBBBBB 1st write 2nd write
A single pixel of data is read after the second write operation as shown, and it is written in the display RAM.
2. 16-bit mode D15, D14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0: RRRRRGGGGGGBBBBB (16 bits) Data is acquired through signal write operation and then written to the display RAM.
(3) Truncated 262K color input mode 1. 8-bit mode D7, D6, D5, D4, D3, D2, D1, D0: RRRRRRXX D7, D6, D5, D4, D3, D2, D1, D0: GGGGGGXX D7, D6, D5, D4, D3, D2, D1, D0: BBBBBBXX 1st write 2nd write 3rd write
A single pixel of data is read after the third write operation as shown, and it is written in the display RAM. "X" is dummy bit, and it is ignored for display.
2. 16 bit mode D15, D14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0: RRRRRRXXGGGGGGXX D15, D14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0: BBBBBBXXXXXXXXXXXX 1st write 2nd write
A single pixel of data is read after the second write operation as shown, and it is written in the display RAM.
Ver 1.5
17/94
2007/01/20
ST7626
(4) Truncated 16M color input mode 1. 8-bit mode D7, D6, D5, D4, D3, D2, D1, D0: RRRRRRRR D7, D6, D5, D4, D3, D2, D1, D0: GGGGGGGG D7, D6, D5, D4, D3, D2, D1, D0: BBBBBBBB 1st write 2nd write 3rd write
A single pixel of data is read after the third write operation as shown, and it is written in the display RAM. 2. 16 bit mode D15, D14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0: RRRRRRRRGGGGGGGG D15, D14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0: BBBBBBBBXXXXXXXX 1st write 2nd write
A single pixel of data is read after the second write operation as shown, and it is written in the display RAM.
7.1.3 8- and 9-bit Serial Interface
The 8-bit serial interface uses four pins /CS, SI, SCL, and A0 to enter commands and data. Meanwhile, the 9-bit serial interface uses three pins /CS, SI and SCL for the same purpose. Data read is not available in the serial interface. Data entered must be 8 bits. Refer to the following chart for entering commands, parameters or gray-scale data. The relation between gray-scale data and data bus in the serial input is the same as that in the 8-bit parallel interface mode at every gradation.
(1) 8-bit serial interface (4-line) When entering data (parameters): A0= HIGH at the rising edge of the 8 SCL.
th
Figure 7.1.3 4-line explaination chart when entering data
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ST7626
When entering command: A0= LOW at the rising edge of the 8 SCL
th
Figure 7.1.4 4-line explaination chart when entering command
(2) 9-bit serial interface (3-line) When entering data (parameters): SI= HIGH at the rising edge of the 1 SCL.
st
Figure 7.1.5 3-line explaination chart when entering data
When entering command: SI= LOW at the rising edge of the 1 SCL.
st
Figure 7.1.6 3-line explaination chart when entering command
If /CS is set to HIGH while the 8 bits from D7 to D0 are entered, the data concerned is invalidated. Before entering succeeding sets of data, you must correctly input the data concerned again. In order to avoid data transfer error due to incoming noise, it is recommended to set /CS at HIGH on byte basis to initialize the serial-to-parallel conversion counter and the register. When executing the command RAMWR, set /CS to HIGH after writing the last address (after starting the 9 pulse in case of 9-bit serial input or after starting the 8 pulse in case of 8-bit serial input).
th th
Ver 1.5
19/94
2007/01/20
ST7626
7.2 ACCESS TO DDRAM AND INTERNAL REGISTERS
ST7626 realizes high-speed data transfer because the access from MPU is a sort of pipeline processing done via the bus holder attached to the internal, requiring the cycle time alone without needing the wait time. For example, when MPU writes data to the DDRAM, the data is once held by the bus holder and then written to the DDRAM before the succeeding write cycle is started. When MPU reads data from the DDRAM, the first read cycle is dummy and the bus holder holds the data read in the dummy cycle, and then it read from the bus holder to the system bus in the succeeding read cycle. Figure 7.2.1 illustrates these relations.
In 80-series interface mode:
M P U sig nal
W rite O peratio n
A0 /W R DATA Interna l signals /W R N D (N ) D (N + 1) D (N + 2) D (N + 3)
B U S H O LD E R AD DRESS CO U NTER
M PU signal
N N
D (N ) N+1
D (N + 1) N+2
D (N + 2) N+3
D (N + 3)
Read O peration
A0 /W R /R D D ATA Internal signals /W R /R D N D um m y D (N ) D (N +1)
BU S H O LD ER AD D R ESS C O U N TE R
N D (N )
D (N ) D (N +1)
D (N +1) D (N +2)
D (N +2) D (N +3)
Figure 7.2.1 Access DDRAM chart
Ver 1.5
20/94
2007/01/20
ST7626
7.3 DISPLAY DATA RAM (DDRAM)
7.3.1 DDRAM
It is 98 X 68 X 16 bits capacity RAM prepared for storing dot data. You can access a desired bit by specifying the page address and column address. Since display data from MCU D7 to D0 and D15 to D8 correspond to one or two pixels of RGB, data transfer related restrictions are reduced, realizing the display flexing. The RAM on ST7626 is separated to a block per 4 lines to allow the display system to process data on the block basis. MPU's read and write operations to and from the RAM are performed via the I/O buffer circuit; Reading of the RAM for the liquid crystal drive is controlled from another separate circuit. Refer to the following memory map for the RAM configuration.
Memory Map (When using the Type A 4096 color. 8-bit mode)
RGB alignment (Command of data control parameter2=000) Data control command (BCH) Column
P11:0(DATCTL) LCD read direction P11:1(DATCTL) Color Data Page Block P10:0
(DATCTL)
0 97 R
D0_7 D0_6 D0_5 D0_4
1 96 B
D1_7 D1_6 D1_5 D1_4
97 0 B
D2_3 D2_2 D2_1 D2_0
G
D0_3 D0_2 D0_1 D0_0
R
D1_3 D1_2 D1_1 D1_0
G
D2_7 D2_6 D2_5 D2_4
R
D146_3 D146_2 D146_1 D146_0-
G
D147_7 D147_6 D147_5 D147_4
B
D147_3 D147_2 D147_1 D147_0
P10:1
(DATCTL)
0
0 1 2 3
67 66 65 64 63 62 61 60 7 6 5 4 3 2 1 0 0 1 2 3 4 5 291 292 293
1
4 5 6 7
15
60 61 62 63
16
64 65 66 67
SEGout
Ver 1.5
21/94
2007/01/20
ST7626
Memory Map (When using the Type A 4096 color. 16-bit mode)
RGB alignment (Command of data control parameter2=000) Data control command (BCH) Column
P11:0(DATCTL) LCD read direction P11:1(DATCTL) Color Data Page Block P10:0
(DATCTL)
0 97 R
D0_15 D0_14 D0_13 D0_12
1 96 B
D0_7 D0_6 D0_5 D0_4
97 0 B
D1_7 D1_6 D1_5 D1_4
G
D0_11 D0_10 D0_9 D0_8
R
D1_15 D1_14 D1_13 D1_12
G
D1_11 D1_10 D1_9 D1_8
R
D97_15 D97_14 D97_13 D97_12
G
D97_11 D97_10 D97_9 D97_8
B
D97_7 D97_6 D97_5 D97_4
P10:1
(DATCTL)
0
0 1 2 3
67 66 65 64 63 62 61 60 7 6 5 4 3 2 1 0 0 1 2 3 4 5 291 292 293
1
4 5 6 7
15
60 61 62 63
16
64 65 66 67
SEGout
Ver 1.5
22/94
2007/01/20
ST7626
Memory Map (When using the Type B 4096 color. 8-bit mode)
RGB alignment (Command of data control parameter2=000) Data control command (BCH) Column
P11:0(DATCTL) LCD read direction P11:1(DATCTL) Color Data Page Block P10:0
(DATCTL)
0 97 R
D0_3 D0_2 D0_1 D0_0
1 96 B
D1_3 D1_2 D1_1 D1_0
97 0 B
D3_3 D3_2 D3_1 D3_0
G
D1_7 D1_6 D1_5 D1_4
R
D2_3 D2_2 D2_1 D2_0
G
D3_7 D3_6 D3_5 D3_4
R
D146_3 D146_2 D146_1 D146_0
G
D147_7 D147_6 D147_5 D147_4
B
D147_3 D147_2 D147_1 D147_0
P10:1
(DATCTL)
0
0 1 2 3
67 66 65 64 63 62 61 60 7 6 5 4 3 2 1 0 0 1 2 3 4 5 291 292 293
1
4 5 6 7
15
60 61 62 63
16
64 65 66 67
SEGout Note:
You can change position of R and B with DATACTL command.
Ver 1.5
23/94
2007/01/20
ST7626
Memory Map (When using the Type B 4096 color. 16-bit mode)
RGB alignment (Command of data control parameter2=000) Data control command (BCH) Column
P11:0(DATCTL) LCD read direction P11:1(DATCTL) Color Data Page Block P10:0
(DATCTL)
0 97 R
D0_11 D0_10 D0_9 D0_8
1 96 B
D0_3 D0_2 D0_1 D0_0
97 0 B
D1_3 D1_2 D1_1 D1_0
G
D0_7 D0_6 D0_5 D0_4
R
D1_11 D1_10 D1_9 D1_8
G
D1_7 D1_6 D1_5 D1_4
R
D97_11 D97_10 D97_9 D97_8
G
D97_7 D97_6 D97_5 D97_4
B
D97_3 D97_2 D97_1 D97_0
P10:1
(DATCTL)
0
0 1 2 3
67 66 65 64 63 62 61 60 7 6 5 4 3 2 1 0 0 1 2 3 4 5 291 292 293
1
4 5 6 7
15
60 61 62 63
16
64 65 66 67
SEGout Note:
You can change position of R and B with DATACTL command.
Ver 1.5
24/94
2007/01/20
ST7626
Memory Map (When using the 65Kcolor. 8-bit mode)
RGB alignment (Command of data control parameter2=000) Data control command (BCH) Column
P11:0(DATCTL) LCD read direction P11:1(DATCTL) Color Data Page Block P10:0
(DATCTL)
0 97 R
D0_7 D0_6 D0_5
1 96 B
D1_4 D1_3 D1_2 D1_1 D1_0
97 0 B
D3_4 D3_3 D3_2 D3_1 D3_0
G
D0_2 D0_1 D0_0 D1_7 D1_6 D1_5
R
D2_7 D2_6 D2_5 D2_4 D2_3
G
D2_2 D2_1 D2_0 D3_7 D3_6 D3_5
R
D146_7 D146_6 D146_5 D146_4 D146_3
G
D146_2 D146_1 D146_0 D147_7 D147_6 D147_5
B
D147_4 D147_3 D147_2 D147_1 D147_0
P10:1
(DATCTL)
D0_4 D0_3
0
0 1 2 3
67 66 65 64 63 62 61 60 7 6 5 4 3 2 1 0 0 1 2 3 4 5 291 292 293
1
4 5 6 7
15
60 61 62 63
16
64 65 66 67
SEGout Note:
You can change position of R and B with DATACTL command.
Ver 1.5
25/94
2007/01/20
ST7626
Memory Map (When using the 65K color. 16-bit mode)
RGB alignment (Command of data control parameter2=000) Data control command (BCH) Column
P11:0(DATCTL) LCD read direction P11:1(DATCTL) Color Data Page Block P10:0
(DATCTL)
0 97 R
D0_15 D0_14 D0_13
1 96 B
D0_4 D0_3 D0_2 D0_1 D0_0
97 0 B
D1_4 D1_3 D1_2 D1_1 D1_0
G
D0_10 D0_9 D0_8 D0_7 D0_6 D0_5
R
D1_15 D1_14 D1_13 D1_12 D1_11
G
D1_10 D1_9 D1_8 D1_7 D1_6 D1_5
R
D97_15 D97_14 D97_13 D97_12 D97_11
G
D97_10 D97_9 D97_8 D97_7 D97_6 D97_5
B
D97_4 D97_3 D97_2 D97_1 D97_0
P10:1
(DATCTL)
D0_12 D0_11
0
0 1 2 3
67 66 65 64 63 62 61 60 7 6 5 4 3 2 1 0 0 1 2 3 4 5 291 292 293
1
4 5 6 7
15
60 61 62 63
16
64 65 66 67
SEGout Note:
You can change position of R and B with DATACTL command.
Ver 1.5
26/94
2007/01/20
ST7626
Memory Map (When using the 262K/16Mcolor. 8-bit mode)
RGB alignment (Command of data control parameter2=000) Data control command (BCH) Column
P11:0(DATCTL) LCD read direction P11:1(DATCTL) Color Data Page Block R
D0_7 D0_6 D0_5 D0_4 D0_3 D0_2 D0_1 D0_0
0 97 G
D1_7 D1_6 D1_5 D1_4 D1_3 D1_2 D1_1 D1_0
1 96 B
D2_7 D2_6 D2_5 D2_4 D2_3 D2_2 D2_1 D2_0
97 0 B
D5_7 D5_6 D5_5 D5_4 D5_3 D5_2 D5_1 D5_0
R
D3_7 D3_6 D3_5 D3_4 D3_3 D3_2 D3_1 D3_0
G
D4_7 D4_6 D4_5 D4_4 D4_3 D4_2 D4_1 D4_0
R
D291_7 D291_6 D291_5 D291_4 D291_3 D291_2 D291_1 D291_0
G
D292_7 D292_6 D292_5 D292_4 D292_3 D292_2 D292_1 D292_0
B
D293_7 D293_6 D293_5 D293_4 D293_3 D293_2 D293_1 D293_0
P10:0
(DATCTL)
P10:1
(DATCTL)
0
0 1 2 3
67 66 65 64 63 62 61 60 7 6 5 4 3 2 1 0 0 1 2 3 4 5 291 292 293
1
4 5 6 7
15
60 61 62 63
16
64 65 66 67
SEGout Note:
You can change position of R and B with DATACTL command.
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27/94
2007/01/20
ST7626
Memory Map (When using the 16 gray-scale, 262K/16M color. 16-bit mode)
RGB alignment (Command of data control parameter2=000) Data control command (BCH) Column
P11:0(DATCTL) LCD read direction P11:1(DATCTL) Color Data Page Block R
D0_15 D0_14 D0_13 D0_12 D0_11 D0_10 D0_9 D0_8
0 97 G
D0_7 D0_6 D0_5 D0_4 D0_3 D0_2 D0_1 D0_0
1 96 B
D1_15 D1_14 D1_13 D1_12 D1_11 D1_10 D1_9 D1_8
97 0 B
D2_7 D2_6 D2_5 D2_4 D2_3 D2_2 D2_1 D2_0
R
D1_7 D1_6 D1_5 D1_4 D1_3 D1_2 D1_1 D1_0
G
D2_15 D2_14 D2_13 D2_12 D2_11 D2_10 D2_9 D2_8
R
D146_7 D146_6 D146_5 D146_4 D146_3 D146_2 D146_1 D146_0
G
D147_15 D147_14 D147_13 D147_12 D147_11 D147_10 D147_9 D147_8
B
D147_7 D147_6 D147_5 D147_4 D147_3 D147_2 D147_1 D147_0
P10:0
(DATCTL)
P10:1
(DATCTL)
0
0 1 2 3
67 66 65 64 63 62 61 60 7 6 5 4 3 2 1 0 0 1 2 3 4 5 291 292 293
1
4 5 6 7
15
60 61 62 63
16
64 65 66 67
SEGout Note:
You can change position of R and B with DATACTL command.
Ver 1.5
28/94
2007/01/20
ST7626
7.3.2 Page Address Control Circuit
This circuit is used to control the address in the page direction when MPU accesses the DDRAM or when reading the DDRAM to display image on the LCD. You can specify a scope of the page address with page address set command. When the page-direction scan is specified with DATACTL command and the address are incremented from the start up to the end page, the column address is incremented by 1 and the page address returns to start page. The DDRAM supports up to 68 lines, and thus the total page becomes 68. In the read operation, as the end page is reached, the column address is automatically incremented by 1 and the page address is returned to start page. Using the address normal/inverse parameter of DATACTL command allows you to inverse the correspondence between the DDRAM address and command output.
7.3.3 Column Address Control Circuit
This circuit is used to control the address in the column direction when MPU accesses the DDRAM. You can specify a scope of the column address using column address set command. When the column-direction scan is specified with DATACTL command and the address are incremented from the start up to the end page, the page address is incremented by 1 and the column address returns to start column. In the read operation, too, the column address is automatically incremented by 1 and returned to start page as the end column is reached. Just like the page address control circuit, using the column address normal/inverse parameter of DATACTL command enables to inverse the correspondence between the DDRAM column address and segment output. This arrangement relaxes restrictions in the chip layout on the LCD module.
7.3.4 I/O Buffer Circuit
It is the bi-directional buffer used when MPU reads or writes the DDRAM. Since MPU's read or write of DDRAM is performed independently from data output to the display data latch circuit, asynchronous access to the DDRAM when the LCD is turned on does not cause troubles such as flicking of the display images.
7.3.5 Block Address Circuit
The circuit associates pages on DDRAM with COM output. ST7626 processes signals for the liquid crystal display on 4-page basis. Thus, when specifying a specific area in the area scroll display or partial display, you must designate it in block.
7.3.6 Display data Latch Circuit
This circuit is used to temporarily hold display data to be output from the DDRAM to the SEG decoder circuit. Since display normal/inverse and display on/off commands are used to control data in the latch circuit alone, they do not modify data in the DDRAM.
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7.4 Area Scroll Display
Using area scroll set and scroll start set commands allows you to scroll the display screen partially. You can select any one of the following four scroll patterns.
Fixed area
Scroll area Figure 7.4.1 Scroll Mode explaination chart
ExampleG In the center screen scroll of 1/48 duty (display range: 48 lines = 12 blocks) Set Area Scroll Block 0 and block 1 (8-lines) are specified for the top fixed area. Top Block Address = Number of the top fixed area = 8 / 4 = 2 (0x0002) Block 15 & block 16 (8-lines) are specified for the bottom fixed area. Block 10 to block 14 (20-lines) are specified for the background area. Bottom Block Address = Number of Background area + Bottom Block Address = (20 / 4) + 9 = 14 (0x000E) Block 2 to Block 9 (32-lines) are specified for the scroll area Number of Specified Blocks = ((Top Fix Area + Scroll Area) - 1) = (2 + (12 - 2 - 2)) - 1 = 9 (0x000E) Set area acroll mode - Center Screen Mode parameter (0x0009) parameter (0x0000) parameter (0x000E) parameter (0x0002) command (0x00AA)
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98 x 68 DDRAM Top Fix (2 Blocks)
0 1 : : : : 9 10 : 15 16
98 x 48(Lines) LCD Panel Time
Scroll Area (7 Blocks)
Background Area (5 Blocks) Bottom Fix (2 Blocks)
DDRAM 0 1 2
LCD Panel
12 blocks =48 lines
9 10
Fixed area 14 15 16 Figure 7.4.2 Reference Example for Scroll Display Background area Scroll area
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7.5 Partial Display
Using partial in command allows you turn on the partial display (division by line) of the screen. This mode requires less current consumption than the whole screen display, making it suitable for the equipment in the standby state.
: Display area (partial display area)
: Non-display area
Figure 7.5.1 Partial Mode explaination chart
If the partial display region is out of the Max. Display range, it would be no operation
-COM0 -COM1 -COM2 -COM3 -COM4 -COM5 -COM6 -COM7 -COM8 -COM9 -COM10 -COM11 -COM12 -COM13 -COM14 -COM15 -COM16 -COM17 -COM18 -COM19 -COM20 -COM21 -COM22 -COM23
Figure 7.5.2 Reference Example for Partial Display
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-COM0 -COM1 -COM2 -COM3 -COM4 -COM5 -COM6 -COM7 -COM8 -COM9 -COM10 -COM11 -COM12 -COM13 -COM14 -COM15 -COM16 -COM17 -COM18 -COM19 -COM20 -COM21 -COM22 -COM23
Figure 7.5.3 Partial Display (Partial Display Duty=16, initial COM0=0)
-COM0 -COM1 -COM2 -COM3 -COM4 -COM5 -COM6 -COM7 -COM8 -COM9 -COM10 -COM11 -COM12 -COM13 -COM14 -COM15 -COM16 -COM17 -COM18 -COM19 -COM20 -COM21 -COM22 -COM23
Figure 7.5.4 Moving Display (Partial Display Duty=16, initial COM0=8)
7.6 Gary-Scale Display
ST7626 incorporates a 4FRC & 31 PWM function circuit to display a 64 gray-scale display.
7.7 Oscillation circuit
This is on-chip Oscillator without external resistor. When the internal oscillator is used, CLS must connect to VDD; when the external oscillator is used, CL could be input pin. This oscillator signal is used in the voltage converter and display timing generation circuit.
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7.8 Display Timing Generator Circuit
This circuit generates some signals to be used for displaying LCD. The display clock, CL (internal), generated by oscillation clock, generates the clock for the line counter and the signal for the display data latch. The line address of on-chip RAM is generated in synchronization with the display clock and the display data latch circuit latches the 68-bits display data in synchronization with the display clock. The display data, which is read to the LCD driver, is completely independent of the access to the display data RAM from the microprocessor. The display clock generates an LCD AC signal (M), which enables the LCD driver to make an AC drive waveform, and also generates an internal common timing signal and start signal to the common driver. The frame signal or the line signal changes the M by setting internal instruction. Driving waveform and internal timing signal are shown in Figure 7.8.1.
Figure 7.8.1 2-frame AC Driving Waveform (Duty Ratio: 1/68)
63
64
1
2
3
4
5
6
7
8
9
10
11
12
55
56
57
58
59
60
61
62
63
64
1
2
3
4
CL(Internal)
FR(Internal) M(Internal)
VLCD V1 V2 V3 V4 Vss VLCD V1 V2 V3 V4 Vss VLCD V1 V2 V3 V4 Vss
COM0
COM1
SEGn
Figure 7.8.2 N-Line Inversion Driving Waveform (N=5, Duty Ratio=1/64)
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7.9 Liquid Crystal drive Circuit
This driver circuit is configured by 68-channel common drivers and 294-channel segment drivers. This LCD panel driver voltage depends on the combination of display data and M signal.
M
COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14
COM0
COM1
COM2
SEG0
SEG 0 1 2 3 4
SEG1
VDD VSS VLCD V1 V2 V3 V4 VSS VLCD V1 V2 V3 V4 VSS VLCD V1 V2 V3 V4 VSS VLCD V1 V2 V3 V4 VSS VLCD V1 V2 V3 V4 VSS
Figure 7.9.1 LCD Driving Waveform
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7.10 Liquid Crystal Driver Power Circuit
The Power Supply circuits generate the voltage levels necessary to drive liquid crystal driver circuits with low power consumption and the fewest components. There are voltage converter circuits, voltage regulator circuits, and voltage follower circuits. They are controlled by power control instruction. For details, refers to "Instruction Description". Table 7.10.1 shows the referenced combinations in using Power Supply circuits.
Table 7.10.1 Recommended Power Supply Combinations Power User setup control (VC VR VF) Only the internal power supply circuits are used Only the voltage regulator circuits and voltage follower circuits are used Only the voltage follower circuits are used Only the external power supply circuits are used 001 OFF OFF ON Open External input Open*1 011 OFF ON ON External input Open*1 Open*1 V/C circuits V/R circuits V/F circuits
VLCD
V0
V1 to V4
a capacitor 111 ON ON ON is series to GND Open*1 Open*1
000
OFF
OFF
OFF
Open
External input
External input
*1 : ST7626 only needs one capacitor series VLCD to GND in normal situation. Add series-capacitors from V0~V4 to GND will improve display performance.
7.10.1 Voltage Converter Circuits
There is a built-in DC-DC voltage converter circuits in ST7626 for generating VLCDOUT. Multiple of voltage converter is 2B 3 4 5 times of Vdd2 toward positive side, and it can be controlled by software(Command ANASET). Please make sure that B B VLCDOUT must below 20V after turn on voltage converter circuit.
7.10.2 Voltage Regulator Circuits
There is a built-in voltage regulaor circuits in ST7626 for generating V0OUT. After VLCDOUT is regulated by voltage regulator circuit, V0OUT is generated. Users also can use VOP function to program the optimum LCD supply voltage V0 by software (Command SETVOP). Detail explaination of VOP-set is listed below: SETVOP Reset state of Vop[8:0] is 160DEC = 10.00V. The VOP value is programmed via the Vop[8:0] register.
V0=a+( Vop[8:6]Vop[5:0])D b
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Ex:VOP[5:0]=100000, VOP[8:6]=010 Vop [8:0]=010100000 3.6+210x0.04=10.00
a is a fixed constant value (see table 7.10.2). b is a fixed constant value (see table 7.10.2). VOP[8:0] is the programmed VOP value. The programming range for VOP[8:0] is 5 to 410 (19Ahex). VOP[5:0] is the set-contrast value which can be set via the command SETVOP and EEPROM.(See command VOLUP & VOLDOWN) The suggested value of V0 is under 11 V with bias =1/9.
Table 7.10.2 SYMBOL a b VALUE 3.6 0.04 UNIT V V
The VOP[8:0] value must be in the VOP programming range as given in Figure 7.10.2. Evaluating equation (1), values outside the programming range indicated in Figure 7.10.2 may result. Calculated values below 4 will be mapped to VOP[8:0] = 4, resulting VOP[8:0] values higher than 410 will be mapped to VOP[8:0] = 410. Sitronix suggestes Vop range equals 4.5V to 18V.
Figure 7.10.2 VOP programming range
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As the programming range for the internally generated V0 voltage is above the limited V0 (18V), users has to ensure while setting the VOP register that under all conditions and including all tolerances that the V0 voltage remains below 18V. Table 7.10.3 Par no. ST7626 Equipment Type Internal Power Supply Thermal Gradient -0.065%/ C @ V0=10.52V, 25 C
0 0
7.10.3 Voltage Follower Circuits
There is a built-in voltage follower circuits in ST7626 for generating V1B V2B V3 and V4. These voltages are decided by bias ratio selection circuitry which is set by users with software to control 1/5 to 1/12 bias ratios to match the optimum display performance of LCD panel. Bias driving rule is listed below: Table 7.10.4 LCD bias 1/N bias V1 (N-1) / N x V0 V2 (N-2) / N x V0 V3 (2/N) x V0 V4 (1/N) x V0
N=5 to 12 7.10.4 The Set-up Power Circuits The ST7626 series has two modes of power circuit. One is 1 CAP with VLCDout, the other is 6 CAP with VLCDout/V0/V1/V2/V3/V4 (depend on panel loading). The detail circuit is as below.
ST7626
Figure 7.10.3 (a) 1 CAP power circuit (b) 6 CAP power circuit
Notes: 1. VLCDout: 1.0~2.2uF/25V 2. V0~V4:0.1~1.0uF/25V
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7.10.5 EEPROM Setting Flow EEPROM Setting Flow
ST7626 provide the Write and Read function to write the Electronic Control value and Built-in resistance ratio into and read them from the built-in EEPROM. Using the Write and Read functions, you can store these values appropriate to each LCD panel. This function is very convenient for user in setting from some different panel's voltage.
Figure 7.10.5 EC value control for different modules by loading EEPROM offset
Note1: This setting flow is used for LCM assembler. Note2: EEPROM shouldn't be written without preceding loading correctly from EEPROM to avoid some errors during IC operation. Note3: When writing value to EEPROM, the voltage of VLCDin must be more than 18V. Note4: When writing value to EEPROM, the voltage of VDD2~VDD5 must be 2.8~3.3V. Note5: When writing value to EEPROM, the Regulator and Follower must turn OFF, and Display also must turn OFF. Note6: If the EEPROM is exposed to a high temperature for hours, data in the memory cell may probably be lost before the data retention guarantee period. To retain data in the memory cell, keep the mamory cell below 90J the retention period. . The data retention guarantee period is specified including
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EEPROM Flow Chart
RESET Internal Initialize
Write( COMMAND , 0x31); Write( COMMAND , 0xF4);
AG Initial Flow
Write( DATA , 0x58);
Show Test Pattern
BG Adjust Vop Offset
EEPROM Operation
CG Write EEPROM
and Booster : ON, Regulator: OFF, Follower: OFF, Display OFF
Load EEPROM
RESET NG Internal Initialize AG Initial Flow
Write( COMMAND , 0x31); Write( COMMAND , 0xF4); Write( DATA , 0x58);
Show Test Pattern
Check If Write Successfully? OK Finish
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Software Program
A. Initial Flow
void ST7626_Init( void ) { Write( COMMAND, 0x30 ); Write( COMMAND, 0x04 ); Write( DATA, 0x3e ); Write( COMMAND, 0x31 ); Write( COMMAND, 0xf4 ); Write( DATA, 0x58 ); Write( COMMAND, 0x30 ); Write( COMMAND, 0x94 ); Write( COMMAND, 0xd1 ); Write( COMMAND, 0xca ); Write( DATA, 0x00 ); Write( DATA, 0x10 ); Write( DATA, 0x00 ); Write( COMMAND, 0x31 ); Write( COMMAND, 0x32 ); Write( DATA, 0x00 ); Write( DATA, 0x02 ); Write( DATA, 0x03 ); Write( DATA, 0x04 ); Write( COMMAND, 0x30 ); Write( COMMAND, 0x81 ); Write( DATA, 0x2d ); Write( DATA, 0x02 ); Write( COMMAND, 0x20 ); Write( DATA, 0x0b ); delay(50000); LoadEEPROM(); LoadPaint(); Write( COMMAND, 0x30 ); Write( COMMAND, 0xa7 ); Write( COMMAND, 0xbb ); Write( DATA, 0x01 ); Write( COMMAND, 0xbc ); Write( DATA, 0x00 ); Write( DATA, 0x00 ); Write( DATA, 0x01 ); Write( COMMAND, 0x75 ); Write( DATA, 0x00 ); Write( DATA, 0x43 ); Write( COMMAND, 0x15 ); Write( DATA, 0x00 ); Write( DATA, 0x5f ); // Ext = 0 // Sleep In/Out Preparation // Sleep In/Out Sequencing // Ext = 1 // Internal Initialize Preparation // Internal Initialize Sequencing // Ext = 0 // Sleep Out // Internal OSC on // Display Control // CL divisions Ratio // Duty Setting (= 68) // N-Line Inverse-set value // Ext = 1 // Analog Setting // OSC Freqency adjustment // Booster Efficiency Setting = Level 3 // Bias Setting (=1/9) // Booster X 5 // Ext = 0 // Electronic Volume Control // EV:Vop[5:0]_6bit // EV:Vop[8:6]_3bit // Vop is 10.52V under this condition for example // Power Control // B/F/R = On/On/On // Delay 50ms // Load EEPROM (refer page 68) // Load Gamma Table Parameter (refer page 64) // Ext = 0 // Inverse Display // Com Scan Direction // 0~33 / 67~34 // Data Scan Direction // Page / Column Address Setting // RGB arrangement (0:RGB 1:BGR) // Gray-scale setup ( 64-gray: 01H) // Page address set // From page address 0 // to page address 67 // Column address set // From column address 0 // to column address 97
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Write( COMMAND, 0xaf ); Write( COMMAND, 0x30 ); } // Display On // Ext = 0
B. Adjust Vop Offset
void adj_Vop_offset(void) { int i,j=1; while(j) { if (KeyScan1==0)i=1; if (KeyScan2==0)i=2; if (KeyScan3==0)i=3; if (KeyScan1==1 & KeyScan2==1 & KeyScan3==1)i=4; switch (i) { Case 1: Write( COMMAND, 0xd6 ); break; case 2: Write( COMMAND, 0xd7 ); break; case 3: write_7626eeprom(); j=0; break; default: break; } } }
// Define KeyScan1 for "D6" use // Define KeyScan2 for "D7" use // Define KeyScan3 for "write" use // Jump to break
// Vop Offset +1 step
// Vop Offset -1 step
// Write EEPROM Flow
C. Write EEPROM
void write_7626eeprom(void) { Write( COMMAND, 0x30 ); Write( COMMAND, 0xae ); Write( COMMAND, 0x20 ); Write( DATA, 0x08 ); Write( COMMAND, 0x31 ); Write( COMMAND, 0xCD ); Write( DATA, 0x20 ); delay(50000); Write( COMMAND, 0xeb ); Write( DATA, 0x00 ); Write( COMMAND, 0xfc ); delay(50000); Write( COMMAND, 0xeb ); Write( DATA, 0x01 );
// EXT=0 // Display Off // Power Control // B/F/R = ON/OFF/OFF // EXT=1 // Enable EEPORM Write Mode //
//Delay 50 ms, the range is delay
// Select EEPROM // EEPROM 1st byte // Write Data to EEPROM // Delay 50ms, the range is 10ms < delay < 80ms // Select EEPROM // EEPROM 2nd byte
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Write( COMMAND, 0xfc ); delay(50000); Write( COMMAND, 0xeb ); Write( DATA, 0x02 ); Write( COMMAND, 0xfc ); delay(50000); Write( COMMAND, 0xeb ); Write( DATA, 0x03 ); Write( COMMAND, 0xfc ); delay(50000); Write( COMMAND, 0xeb ); Write( DATA, 0x04 ); Write( COMMAND, 0xfc ); delay(50000); Write( COMMAND, 0xcc ); delay(50000); Write( COMMAND, 0x30 ); Write( COMMAND, 0x20 ); Write( DATA, 0x0b ); Write( COMMAND, 0xaf ); } // Write Data to EEPROM
//Delay 50 ms, the range is delay
// Select EEPROM // EEPROM 3rd byte // Write Data to EEPROM // Delay 50ms, the range is 10ms < delay < 80ms // Select EEPROM // EEPROM 4th byte // Write Data to EEPROM // Delay 50ms, the range is 10ms < delay < 80ms // Select EEPROM // EEPROM 5th byte // Write Data to EEPROM // Delay 50ms, the range is 10ms < delay < 80ms // Cancel EEPROM // Delay 50ms // EXT=0 // Power Control // B/F/R = On/On/On // Display On
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7.11 RESET CIRCUIT
When the RST pin reveives a negative reset pulse all internal circuitry will start to initialize. The minimum pulse width for completing the reset sequence is 3 us at Vdd=1.8V. The ststus of ST7626 after reset flow is listed below:
When Power is turned on Input power (VDD1~VDD5) Be sure to apply POWER-ON RESET (RESET=LOW) < Display Setting 1 > Display control (DISCTL) Setting clock dividing ratio: Duty setting: Setting reverse rotation number of line: Common scan direction (COMSCN) Setting scan direction: Oscillation on (OSCON): Sleep-out (SLIPOUT): < Power Supply Setting > Electronic volume control (VOLCTR) Setting volume value: Setting built-in resistance value: Power control (PWRCTR) Setting operation of power supply circuit: < Display Setting 2 >
Normal rotation of display (DISNOR) / inversion of display (DISINV): COM0 COM33, COM34 COM67
<< State after reset >> 2 divisions 1/4 11H reverse rotations
Oscillation off Sleep-in
<< State after reset >> 0 0 (3.76) ALL OFF
<< State after reset >> Normal rotation of display Partial-out 0 0 Full-screen scroll 0
Partial-in (PTLIN) / Partial-out (PLOUT): Setting fix area: Area scroll set (ASCSET) Setting area scroll region: Setting area scroll type: Scroll start set (SCSTART) Setting scroll start address: < Display Setting 3 > Data control (DATCTL)
<< State after reset >>
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Setting normal radiation / inversion of page address: Setting normal radiation / inversion of column address: Setting direction of address scanner: Setting RGB arrangement: Setting gradation: 65K-color position set (RGBSET8) Setting color position at 65K-color: < RAM Setting > Page address set (PASET) Setting start page address: Setting end page address: Column address set (PASET) Setting start column address: Setting end column address: < RAM Write > Memory write command (RAMWR) Writing displayed data: repeat as many as the number needed and exit by entering other command. < Waiting (approximately 100ms) > Wait until the power supply voltage has stabilized. Enter the power supply control command first, then wait at least 100ms before entering the Display ON command when the built-in power supply circuit operates. If you do not wait, an unwanted display may appear on the liquid crystal panel. Display on (DISON): Display off << State after reset >> 0 0 0 0 << State after reset >> All 0 Normal rotation Normal rotation Column direction RGB 65K
Note: If changes are unnecessary after reset, command input is unnecessary.
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8. COMMANDS
8.1 Command table
Ext=0 Command DISON DISOFF DISNOR DISINV COMSCN DISCTR SLPP SLPIN SLPOUT PASET CASET DATCTL RAMWR RAMRD PLTIN PLTOUT RMWIN RMWOUT ASCSET SCSTART OSCON OSCOFF PWRCTL VOLCTR VOLUP VOLDOWN STREAD EPSRRD1 EPSRRD2 NOP EEOK RESERVED A0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RD 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 WR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 1 1 1 0 0 D7 1 1 1 1 1 1 0 1 1 0 0 1 0 0 1 1 1 1 1 1 1 1 0 1 1 1 D6 0 0 0 0 0 1 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D5 1 1 1 1 1 0 0 0 0 1 0 1 0 0 1 1 1 1 1 1 0 0 1 0 0 0 D4 0 0 0 0 1 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 0 0 1 1 D3 1 1 0 0 1 1 0 0 0 0 0 1 1 1 1 1 0 1 1 1 0 0 0 0 0 0 D2 1 1 1 1 0 0 1 1 1 1 1 1 1 1 0 0 0 1 0 0 0 0 0 0 1 1 D1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 0 0 1 1 D0 1 0 0 1 1 0 0 1 0 1 1 0 0 1 0 1 0 0 0 1 1 0 0 1 0 1 Function Display On Display Off Normal Display Inverse Display Com Scan Direction Display Control Sleep In/Out Preparation Sleep In Sleep Out Page Address Set Column Address Set Data Scan Direction Writing to Memory Reading from Memory Partial display in Partial display out Read Modify Write In Read Modify Write Out Area Scroll Set Scroll Start Set Internal OSC on Internal OSC off Power Control EC control EC increase 1 EC decrease 1 Status Read 1 1 1 1 0 0 0 0 1 1 0 1 1 1 0 READ Register1 READ Register2 NOP Instruction EEPROM Function Start Not Use 7C 7D 25 07 82 None None None 1 byte 28 29 30 31 32 Hex Parameter Index AF AE A6 A7 BB CA 04 95 94 75 15 BC 5C 5D A8 A9 E0 EE AA AB D1 D2 20 81 D6 D7 None None None None 1 byte 3 byte 1 byte None None 2 byte 2 byte 3 byte Data Data 2 byte None None None 4 byte 1 byte None None 1 byte 2 byte None None 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
Status Read 1 1 0 0 0 1 1 0 0 0
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Ext=1 Command Frame1 Set Frame2 Set Frame3 Set Frame4 Set ANASET EPCTIN EPCOUT EPMWR EPMRD DISPADJ A0 0 0 0 0 0 0 0 0 0 0 RD 1 1 1 1 1 1 1 1 1 1 WR 0 0 0 0 0 0 0 0 0 0 D7 0 0 0 0 0 1 1 1 1 1 D6 0 0 0 0 0 1 1 1 1 1 D5 1 1 1 1 1 0 0 1 1 1 D4 0 0 0 0 1 0 0 1 1 1 D3 0 0 0 0 0 1 1 1 1 1 D2 0 0 0 0 0 1 1 1 1 0 D1 0 0 1 1 1 0 0 0 0 1 D0 0 1 0 1 0 1 0 0 1 0 Function FRAME 1 PWM Set FRAME 2 PWM Set FRAME 3 PWM Set FRAME 4 PWM Set Analog Set Control EEPROM Cancel EEPROM Write to EEPROM Read from EEPROM Display Performance Adjustment Internal Initialize Preparation Hex Parameter Index 20 21 22 23 32 CD CC FC FD FA 16 byte 16 byte 16 byte 16 byte 3 byte 1 byte None None None 1 byte 1 2 3 4 5 6 7 8 9 10
IIPP
0
1
0
1
1
1
1
0
1
0
0
F4
1 byte
11
Ext=1 or Ext=0 Command Ext In Ext Out A0 0 0 RD 1 1 WR 0 0 D7 0 0 D6 0 0 D5 1 1 D4 1 1 D3 0 0 D2 0 0 D1 0 0 D0 0 1 Function Ext=0 Set Ext=1 Set Hex Parameter Index 30 31 None None ---
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8.2 EXT="0" Function Description
(1) Display ON (DISON) Command: 1; Parameter: None (AFH) It is used to turn the display on. When the display is turned on, segment outputs and common outputs are generated at the level corresponding to the display data and display timing. You can't turn on the display as long as the sleep mode is selected. Thus, whenever using this command, you must cancel the sleep mode first. A0 Command 0 RD 1 WR 0 D7 1 D6 0 D5 1 D4 0 D3 1 D2 1 D1 1 D0 1
(2) Display OFF (DISOFF) Command: 1; Parameter: None (AEH) It is used to forcibly turn the display off. As long as the display is turned off, every on segment and common outputs are forced to VSS level. A0 Command 0 RD 1 WR 0 D7 1 D6 0 D5 1 D4 0 D3 1 D2 1 D1 1 D0 0
(3) Normal display (DISNOR) Command: 1; Parameter: None (A6H) It is used to normally highlight the display area without modifying contents of the display data RAM. A0 Command 0 RD 1 WR 0 D7 1 D6 0 D5 1 D4 0 D3 0 D2 1 D1 1 D0 0
(4) Inverse display (DISINV) Command: 1; Parameter: None (A7) It is used to inversely highlight the display area without modifying contents of the display data RAM. This command does not invert non-display areas in case of using partial display. A0 Command 0 RD 1 WR 0 D7 1 D6 0 D5 1 D4 0 D3 0 D2 1 D1 1 D0 1
(5) Common scan (COMSCAN) Command: 1; Parameter: 1 (BBH) It is used to specify the common output direction in the pin of CSEL = L. This command helps increasing degrees of freedom of wiring on the LCD panel. A0 Command Parameter1 (P1) 0 RD 1 WR 0 0 D7 1 * D6 0 * D5 1 * D4 1 * D3 1 * D2 0 P12 D1 1 P11 D0 1 P10 Function Command Scan direction
When CSEL=0 configuration is selected, pins and common outputs are scanned in the order shown below. P12 0 0 0 0 P11 0 0 1 1 P10 0 1 0 1 Common scan direction COM0 pin 0 0 33 33 COM33 pin 33 33 0 0 COM34 pin 34 67 34 67 COM67 pin 67 34 67 34
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Common scan direction
Original graphic:
Com0
Com34
Com33
Com67
P12:P11:P10:0:0:0 (0 33, 34 67) P12:P11:P10:0:0:1 (0 33, 67 34)
Com0
Com0
Com34
Com33
Com67
Com33
Com67
Com34
P12:P11:P10:0:1:0 (33 0, 34 67)
P12:P11:P10:0:1:1 (33 0, 67 34)
Com33
Com33
Com34
Com0
Com67
Com0
Com67
Com34
(6) Display control (DISCTL) Command: 1; Parameter: 3 (CAH) This command and succeeding parameters are used to perform the display timing-related setups. This command must be selected before using SLPOUT. Don't change this command while the display is turned on. A0 Command Parameter1(P1) Parameter2(P2) Parameter3(P3) 0 1 1 1 RD 1 1 1 1 WR 0 0 0 0 D7 1 * * 0 D6 1 * * P36 D5 0 * * P35 D4 0 P14 P24 P34 D3 1 P13 P23 P33 D2 0 P12 P22 P32 D1 1 * P21 P31 D0 0 * Function CL dividing ratio, F1 and F2 drive pattern.
P20 Drive duty P30 FR inverse-set value
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P1: it is used to specify the CL dividing ratio. P14, P13, P12: CL dividing ratio. They are used to change number of dividing stages of external or internal clock. P14 0 0 0 0 P13 0 0 1 1 P12 0 1 0 1 CL dividing ratio Not divide 2 divisions 4 divisions 8 divisions
P2: It is used to specify the duty of the module on block basis. Duty Example: 1/68 duty * 0 * 0 * 0 P24 0 P23 1 P22 1 P21 1 P20 1 (Numbers of display lines)/4-1 64/4-1=15
This will output driving voltage waveforms from com0 to com63. P3: It is used to specify number of lines to be inversely highlighted on LCD panel from P36 to P30 (lines can be inversely highlighted in the range of 2 to 64) Inversely highlighted line Example: 0AH Example: 7CH P37 0 0 P36 0 1 P35 0 1 P34 0 1 P33 1 1 P32 0 1 P31 1 0 P30 0 0 Inversely highlighted lines-1 11 (lines)-1 = 10 (lines) 61 (lines)-1 = 60 (lines)
P34="0": Frame inversion occurs every frame; P34="1": Independent from frames. In the default, 0 inverse highlighted line is selected.
(7) Sleep In/Out Preparation (SLPP) Command: 1; Parameter: 1 Using this command to setup ready status for sleep-in or sleep out. A0 Command Parameter(P1) 0 1 RD 1 1 RW 0 0 D7 0 0 D6 0 0 D5 0 1 D4 0 1 D3 0 1 D2 1 1 D1 0 1 D0 0 P10 Function Sleep in/out ready
P10 =" 1": Ready for sleep in. P10 = "0": Ready for sleep out. Parameter 3FH is used to initialize sleep-in sequencing, and parameter 3EH is used to initialize sleep-out sequencing.
(8) Sleep in (SPLIN) Command: 1; Parameter: None (95H) A0 Command 0 RD 1 WR 0 D7 1 D6 0 D5 0 D4 1 D3 0 D2 1 D1 0 D0 1
(9) Sleep out (SLPOUT) Command: 1; Parameter: None (94H) A0 Command 0 RD 1 WR 0 D7 1 D6 0 D5 0 D4 1 D3 0 D2 1 D1 0 D0 0
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(10) Page address set (PASET) Command: 1; Parameter: 2 (75H) When MPU makes access to the display data RAM, this command and succeeding parameters are used to specify the page address area. As the addresses are incremented from the start to the end page in the page-direction scan, the column address is incremented by 1 and the page address is returned to the start page. Note: that the start and end page must be specified as a pair. Also, the relation "start page < end page" must be maintained. A0 Command Parameter1(P1) Parameter2(P2) 0 1 1 RD 1 1 1 WR 0 0 0 D7 0 * * D6 1 P16 P26 D5 1 P15 P25 D4 1 P14 P24 D3 0 P13 P23 D2 1 P12 P22 D1 0 P11 P21 D0 1 P10 P20 Function Start page End page
(11) Column address set (CASET) Command: 1; Parameter: 2 (15H) When MPU makes access to the display data RAM, this command and succeeding parameters are used to specify the column address area. As the addresses are incremented from the start to the end column in the column-direction scan, the page address is incremented by 1 and the column address is returned to the start column. Note: that the start and end column must be specified as a pair. Also, the relation "start column < end column" must be maintained. A0 Command Parameter1(P1) Parameter2(P2) 0 1 1 RD 1 1 1 WR 0 0 0 D7 0 * * D6 0 P16 P26 D5 0 P15 P25 D4 1 P14 P24 D3 0 P13 P23 D2 1 P12 P22 D1 0 P11 P21 D0 1 P10 P20 Function Start address End address
(12) Data control (DATCTL) Command: 1; Parameter: 3 (BCH) This command and succeeding parameters are used to perform various setups needed when MPU operates display data stored on the built-in RAM. A0 Command 0 RD 1 WR 0 D7 1 D6 0 D5 1 D4 1 D3 1 D2 1 D1 0 D0 0 Function Normal/inverse display of Parameter1(P1) 1 1 0 * * * * * P12 P11 P10 page/column address and address scan direction. Parameter2(P2) Parameter3(P3) 1 1 1 1 0 0 * * * * * * * * * * * P32 * P31 P20 RGB arrangement P30 Gray-scale setup
P1: It is used to specify the normal or inverse display of the page / column address and also to specify the address scanning direction. P10: Normal/inverse display of the page address. P10=0: Normal and P10=1: Inverse P11: Normal/reverse turn of column address. P11=0: Normal rotation and P11=1: Reverse rotation. P12: Address-scan direction. P12=0: In the column direction and P12=1: In the page direction.
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Page address and page-address scan direction
P12=0 Column direction P11=0 P11=1 P10=0 0 1 2 0 97 P10=1 67 66 65 1 96 2 95 95 2 96 1 97 0
65 66 67 P12=1 Page direction P11=0 P11=1 P10=0 0 1 2
2 1 0 0 97 P10=1 67 66 65 1 96 2 95 95 2 96 1 97 0
65 66 67
2 1 0
P2: RGB arrangement. This parameter allows you to change RGB arrangement of data which is going to be written into RAM, and therefore causes the inverse RGB rotation of the segment output of ST7626. You can fit RGB arrangement on the LCD panel according to this parameter setting. P20 0 1 SEG0 R B SEG1 G G SEG2 B R SEG3 R B SEG4 G G SEG5 B R SEG6 R B SEG7 G G ... ... ... SEG293 B R
P3: Gray scale setup. Using this parameter, you can select the 4K, 65K, 262K, and 16M display mode depending on the difference in RGB data arrangement. P32 0 0 1 1 1 P31 0 1 0 0 1 P30 1 0 0 1 0 Numbers of gray-scale 64-gray 65K 64-gray 262K 64-gray 16M 16-gray 4K Type A 16-gray 4K Type B
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(13) Memory write (RAMWR) Command: 1; Parameter: Numbers of data written (5CH) When MPU writes data to the display memory, this command turns on the data entry mode. Entering this command always sets the page and column address at the start address. You can rewrite contents of the display data RAM by entering data succeeding to this command. At the same time, this operation increments the page or column address as applicable. The write mode is automatically cancelled if any other command is entered. 1. 8-bit bus A0 Command Parameter 2. 16-bit bus A0 Command parameter 0 1 RD 1 1 RW 0 0 D15 * D14 * ... ... D9 * D8 * D7 0 D6 1 D5 0 D4 1 D3 1 D2 1 D1 0 D0 0 Function Memory write Write data 0 1 RD 1 1 RW 0 0 D7 0 D6 1 D5 0 D4 1 D3 1 D2 1 D1 0 D0 0 Function Data to be written
Data to be written
Data to be written
(14) Memory read (RAMRD) Command: 1; Parameter: Numbers of data read (5DH) When MPU read data from the display memory, this command turns on the data read mode. Entering this command always sets the page and column address at the start address. After entering this command, you can read contents of the display data RAM. At the same time, this operation increments the page or column address as applicable. The data read mode is automatically cancelled if any other command is entered. 1. 8-bit bus A0 Command Parameter 2. 16-bit bus A0 Command parameter 0 1 RD 1 0 RW 0 1 D15 * D14 * .... * D9 * D8 * D7 0 D6 1 D5 0 D4 1 D3 1 D2 1 D1 0 D0 1 Function Memory read Read data 0 1 RD 1 0 RW 0 1 D7 0 D6 1 D5 0 D4 1 D3 1 D2 1 D1 0 D0 1 Function Data to be read
Data to be read
Data to be read
(15) Partial in (PTLIN) Command: 1; Parameter: 2 (A8H) This command and succeeding parameters specify the partial display area. This command is used to turn on partial display of the screen (dividing screen by lines) in order to save power. Since ST7626 processes the liquid crystal display signal on 4-line basis (block basis), the display and non-display areas are also specified on 4-bit line (block basis). A0 Command Parameter(P1) Parameter(P2) 0 1 1 RD 1 1 1 RW 0 0 0 D7 1 * * D6 0 * * D5 1 * * D4 0 P14 P24 D3 1 P13 P23 D2 0 P12 P22 D1 0 P11 P21 D0 0 P10 P20 Function Start block address End block address
A block address that can be specified for the partial display must be the display one (don't try to specify an address not to be displayed when scrolled).
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(16) Partial out (PTLOUT) Command: 1; Parameter: 0 (A9H) This command is used to exit from the partial display mode. A0 Command 0 RD 1 RW 0 D7 1 D6 0 D5 1 D4 0 D3 1 D2 0 D1 0 D0 1
(17) Read modify write in (RMWIN) Command: 1; Parameter: 0 (E0H) This command is used along with the column address set command, page address set command and read modify write out command. This function is used when frequently modifying data to specify a specific display area such as blinking cursor. First set a specific display area using the column and page address commands. Then, enter this command to set the column and page addresses at the start address of the specific area. When this operation is complete, the column (page) address won't be modified by the display data read command. It is incremented only when the display data write command is used. You can cancel this mode by entering the read modify write out or any other command.
A0 Command 0
RD 1
RW 0
D7 1
D6 1
D5 1
D4 0
D3 0
D2 0
D1 0
D0 0
(18) Read modify write out (RMWOUT) Command: 1; Parameter: 0 (EEH) Enter this command cancels the read modify write mode A0 Command 0 RD 1 RW 0 D7 1 D6 1 D5 1 D4 0 D3 1 D2 1 D1 1 D0 0
(19) Area scroll set (ASCSET) Command: 1; Parameter: 4 (AAH) It is used when scrolling only the specified portion of the screen (dividing the screen by lines). This command and succeeding parameters specify the type of area scroll, fix area and scroll area. A0 Command Parameter(P1) Parameter(P2) Parameter(P3) Parameter(P4) 0 1 1 1 1 RD 1 1 1 1 1 RW 0 0 0 0 0 D7 1 * * * * D6 0 * * * * D5 1 * * * * D4 0 P14 P24 P34 * D3 1 P13 P23 P33 * D2 0 P12 P22 P32 * D1 1 P11 P21 P31 P41 D0 0 P10 P20 P30 P40 Function Top block address Bottom block address Number of specified blocks Area scroll mode
P4: It is used to specify an area scroll mode. P41 0 0 1 1 P40 0 1 0 1 Type of area scroll Center screen scroll Top screen scroll Bottom screen scroll Whole screen scroll
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Center screen scroll Top screen scroll Bottom screen scroll Whole screen scroll
Fixed area
Scroll area
Since ST7626 processes the liquid crystal display signals on the four-line basis (block basis), FIX and scroll areas are also specified on the four-line basis (block basis). DDRAM address corresponding to the top FIX area is set in the block address incrementing direction starting with 0 block. DDRAM address corresponding to the bottom FIX area is set in the block address decreasing direction starting with 16 block. Other DDRAM blocks excluding the top and bottom FIX areas are assigned to the scroll + background areas. P1: It is used to specify the top block address of the scroll + background areas. Specify the 0 block for the top screen scroll or whole screen scroll. P2: It specifies the bottom address of the scroll+ background areas. Specify the 16 block for the bottom or whole screen scroll. Required relation between the start and end blocks (top block addressth th st
You can turn on the area scroll function by executing the area scroll set command first and then specifying the display start block of the scroll area with the scroll start set command. [Area Scroll Setup Example] In the center screen scroll of 1/48 duty (display range: 48 lines = 12 blocks), if 8 lines = 2 blocks and 8 lines = 2 blocks are specified for the top and bottom FIX areas, 36 lines = 9 blocks is specified for the scroll areas, respectively, 16 lines = 4 blocks on the DDRAM are usable as the background area. Value of each parameter at this time is as shown below.
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A0 P1 P2 P3 P4 1 1 1 1 RD 1 1 1 1 RW 0 0 0 0 D7 * * * * D6 * * * * D5 * * * * D4 0 0 0 * D3 0 1 1 * D2 0 1 1 * D1 1 1 0 0 D0 0 0 0 0 Top block address = 02 H Bottom block address = 0E H Number of specific blocks = 09 H Area scroll mode = center
(20) Scroll start address set (SCSTART) Command:1 Parameter: 1 (ABH) This command and succeeding parameters are used to specify the start block address of the scroll area. Note: that you must execute this command after executing the area scroll set command. Scroll becomes available by dynamically changing the start block address. A0 Command Parameter(P1) 0 1 RD 1 1 RW 0 0 D7 1 * D6 0 * D5 1 * D4 0 P14 D3 1 P13 D2 0 P12 D1 1 P11 D0 1 P10 Function Start block address
(21) Internal oscillation on (OSCON) Command: 1; Parameter: 0 (D1H) This command turns on the internal oscillation circuit. It is valid only when the internal oscillation circuit of CLS = HIGH is used. A0 Command 0 RD 1 RW 0 D7 1 D6 1 D5 0 D4 1 D3 0 D2 0 D1 0 D0 1
(22) Internal oscillation off (OSOFF) Command: 1; Parameter: 0 (D2H) It turns off the internal oscillation circuit. This circuit is turned off in the reset mode. A0 Command 0 RD 1 RW 0 D7 1 D6 1 D5 0 D4 1 D3 0 D2 0 D1 1 D0 0
(23) Power control set (PWRCTR) Command: 1; Parameter: 1 (20H) This command is used to turn on or off the Booster circuit, follower voltage, and voltage regulator circuit. A0 Command Parameter(P1) 0 1 RD 1 1 RW 1 0 D7 0 * D6 0 * D5 1 * D4 0 0 D3 0 P13 D2 0 0 D1 0 P11 D0 0 P10 Function LCD drive power
P10: It turns on or off the voltage regulator voltage. P10 = "1": ON. P10 =" 0": OFF P11: It turns on or off the follower circuit. P11 = "1": ON. P11 =" 0": OFF P13:It turns on or off the Booster. P13 = "1": ON. P13 =" 0": OFF
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(24) Electronic volume control (VOLCTR) Command: 1; Parameter: 2 (81H)
The command is used to program the optimum LCD supply voltage VOP. Reference to 7.10.2
A0 Command Parameter(P1) Parameter(P2) 0 1 1 RD 1 1 1 RW 0 0 0 D7 1 * * D6 0 * * D5 0 P15 * D4 0 P14 * D3 0 P13 * D2 0 P12 P18 D1 0 P11 P17 D0 1 P10 P16 Function Set Vop[5:0] Set Vop[8:6]
(25) Increment electronic control (VOLUP) Command: 1; Parameter: 0 (D6H)
With the VOLUP and VOLDOWN command the VOP voltage and therewith the contrast of the LCD can be adjusted.
This command increments electronic control value Vop[5:0] of voltage regulator circuit by 1. A0 Command 0 RD 1 RW 0 D7 1 D6 1 D5 0 D4 1 D3 0 D2 1 D1 1 D0 0
If you set the electronic control value to 111111, the control value is set to 000000 after this command has been executed.
(26) Decrement electronic control (VOLDOWN) Command: 1; Parameter: 0 (D7H)
With the VOLUP and VOLDOWN command the VOP voltage and therewith the contrast of the LCD can be adjusted.
This command decrements electronic control value Vop[5:0] of voltage regulator circuit by 1.
A0 Command 0
RD 1
RW 0
D7 1
D6 1
D5 0
D4 1
D3 0
D2 1
D1 1
D0 1
If you set the electronic control value to 000000, the control value is set to 111111 after this command has been executed.
Table 8.1.1 Possible Vop[5:0] values
Electronic Control Value Decimal Equivalent 31 30 29 ... 2 1 0 -1 -2 ... -30 -31 -32 VOP Offset
111111
111110 111101 ...
+1240 mV +1200 mV +1160 mV
...
000010 000001 000000
111111
+80 mV +40 mV 0 mV -40 mV -80 mV
... -1200 mV -1240 mV -1280mV
111110
...
100010
100001 100000
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(27) Status read (STREAD) Command: 1; Parameter: None It is the command for reading the internal condition of the IC. A0 Command 0 RD 0 RW 1 D7 D6 D5 D4 D3 D2 D1 D0
(8) Status data
Issue STREAD (Status Read) command is only for reading the internal condition of the IC. One status data can be displayed depending on the setting. Issue the NOP command after the STREAD (Status Read) command. The Status data will be composed of 8 bits below:
D7: Area scroll mode D6: Area scroll mode D5: RMW on/off D4: Scan direction D3: Display ON/OFF D2: EEPROM access D1: Display normal/inverse D0: Partial display
Refer to P41 (ASCSET) Refer to P40 (ASCSET) 0 : Out 0 : Column 0 : OFF 0: OutAccess 0 : Normal 0 : OFF 1 : In 1 : Page 1 : ON 1: InAccess 1 : Inverse 1 : ON
(28) Read Register 1 (EPSRRD1) Command: 1; Parameter: 0 (7CH) It is the command for reading the Electronic Control values. A0 Command 0 RD 1 RW 0 D7 0 D6 1 D5 1 D4 1 D3 1 D2 1 D1 0 D0 0
Issue the EPSRRD1 and then STREAD (Status Read) commands in succession to read the Electronic Control values. One status data can be displayed depending on the setting. Also, always issue the NOP command after the STREAD (Status Read) command.
The Status data will be composed of 8 bits below: D7: 0 D6: 0 D[5:0]: Vop[5:0] Refer to electronic volume control values Vop[5:0]
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(29) Read Register 2 (EPSRRD2) Command: 1 ;Parameter: 0 (7DH) It is the command for reading ID codes of the ST7626 and the built-in resistance ratio. A0 Command 0 RD 1 RW 0 D7 0 D6 1 D5 1 D4 1 D3 1 D2 1 D1 0 D0 1
Issue the EPSRRD2 and then STREAD (Status Read) commands in succession to read IC's ID and the built-in resistance ratio. One status data can be displayed depending on the setting. Also, always issue the NOP command after the STREAD (Status Read) command. The Status data will be composed of 8 bits below: D[7:3]: ST7626 ID codes D[2:0]: Vop[8:6] 00010 Refer to the built-in resistance ratio Vop[8:6]
(30) Non-operating (NOP) Command: 1; Parameter: 0 (25H) This command does not affect the operation. A0 Command 0 RD 1 RW 0 D7 0 D6 0 D5 1 D4 0 D3 0 D2 1 D1 0 D0 1
This command, however, has the function of canceling the IC test mode. Thus, it is recommended to enter it periodically to prevent malfunctioning due to noise and such.
(31) EEPROM Function Start (EEOK) Command:1;Parameter:1(07H) In the EEPROM read/write flow, EEPROM is ready after issuing this command. Its parameter is set to 19H. A0 Command Parameter(P1) 0 1 RD 1 1 RW 0 0 D7 0 0 D6 0 0 D5 0 0 D4 0 1 D3 0 1 D2 1 0 D1 1 0 D0 1 1 Function 19H
(32) Reserved (82H) Do not use this command A0 Command 0 RD 1 RW 0 D7 1 D6 0 D5 0 D4 0 D3 0 D2 0 D1 1 D0 0
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8.3 EXT="1" Function Description
(1) Set Frame1 value (Frame1 set) Command: 1; Parameter: 16 (20H) Command Frame1 Set A0 0 RD 1 WR 0 D7 0 D6 0 D5 1 D4 0 D3 0 D2 0 D1 0 D0 0 Function FRAME 1 PWM Set
A0 Command Parameter1(P1) Parameter2(P2) 0 1 1
RD 1 1 1
WR 0 0 0
D7 0 * *
D6 0 * *
D5 1 * *
D4 0
D3 0
D2 0
D1 0
D0 0
Function
P14 P13 P12 P11 P10 Set RGB level 0 of 1st frame P24 P23 P22 P21 P20 Set RGB level 1 of 1st frame
Parameter15(P15) Parameter16(P16)
1 1
1 1
0 0
* *
* *
* *
P154 P153 P152 P151 P150 Set RGB level 14 of 1st frame P164 P163 P162 P161 P160 Set RGB level 15 of 1st frame
(2)Set Frame2 value (Frame2 set) Command: 1; Parameter: 16 (21H) Command Frame2 Set A0 0 RD 1 WR 0 D7 0 D6 0 D5 1 D4 0 D3 0 D2 0 D1 0 D0 1 Function FRAME 2 PWM Set
A0 Command Parameter1(P1) Parameter2(P2) 0 1 1
RD 1 1 1
WR 0 0 0
D7 0 * *
D6 0 * *
D5 1 * *
D4 0
D3 0
D2 0
D1 0
D0 0
Function
P14 P13 P12 P11 P10 Set RGB level 0 of 2nd frame P24 P23 P22 P21 P20 Set RGB level 1 of 2nd frame
Parameter15(P15) Parameter16(P16)
1 1
1 1
0 0
* *
* *
* *
P154 P153 P152 P151 P150 Set RGB level 14 of 2nd frame P164 P163 P162 P161 P160 Set RGB level 15 of 2nd frame
(3) Set Frame3 value (Frame3 set) Command: 1; Parameter: 16 (22H) Command Frame3 Set A0 0 RD 1 WR 0 D7 0 D6 0 D5 1 D4 0 D3 0 D2 0 D1 1 D0 0 Function FRAME 3 PWM Set
A0 Command Parameter1(P1) Parameter2(P2) 0 1 1
RD 1 1 1
WR 0 0 0
D7 0 * *
D6 0 * *
D5 1 * *
D4 0
D3 0
D2 0
D1 0
D0 0
Function
P14 P13 P12 P11 P10 Set RGB level 0 of 3rd frame P24 P23 P22 P21 P20 Set RGB level 1 of 3rd frame
Parameter15(P15) Parameter16(P16)
1 1
1 1
0 0
* *
* *
* *
P154 P153 P152 P151 P150 Set RGB level 14 of 3rd frame P164 P163 P162 P161 P160 Set RGB level 15 of 3rd frame
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(4) Set Frame4 value (Frame4 set) Command: 1; Parameter: 16 (23H) Command Frame4 Set A0 0 RD 1 WR 0 D7 0 D6 0 D5 1 D4 0 D3 0 D2 0 D1 1 D0 1 Function FRAME 4 PWM Set
A0 Command Parameter1(P1) Parameter2(P2) 0 1 1
RD 1 1 1
WR 0 0 0
D7 0 * *
D6 0 * *
D5 1 * *
D4 0
D3 0
D2 0
D1 0
D0 0
Function
P14 P13 P12 P11 P10 Set RGB level 0 of 4th frame P24 P23 P22 P21 P20 Set RGB level 1 of 4th frame
Parameter15(P15) Parameter16(P16)
1 1
1 1
0 0
* *
* *
* *
P154 P153 P152 P151 P150 Set RGB level 14 of 4th frame P164 P163 P162 P161 P160 Set RGB level 15 of 4th frame
The default value of RGB level set FRAM1 SET RGB level0 RGB level1 RGB level2 RGB level3 RGB level4 RGB level5 RGB level6 RGB level7 RGB level8 RGB level9 RGB level10 RGB level11 RGB level12 RGB level13 RGB level14 RGB level15 00 02 04 06 08 0A 0C 0E 10 12 14 16 18 1A 1C 1E FRAM2 SET 00 02 04 06 08 0A 0C 0E 10 12 14 16 18 1A 1C 1E FRAM3 SET 00 02 04 06 08 0A 0C 0E 10 12 14 16 18 1A 1C 1E FRAME4 SET 00 02 04 06 08 0A 0C 0E 10 12 14 16 18 1A 1C 1E
All the modulation range of each level for each frame is from 00'H to 1F'H.
ExampleG Paint setup
void LoadPaint( void ) { Write( COMMAND, 0x0031 ); Write( COMMAND, 0x0020 ); Write( DATA, 0x0000 ); Write( DATA, 0x0002 ); Write( DATA, 0x0005 ); // Ext = 1 // Palette FRC1 Setup // RGB Level0 Setup // RGB Level1 Setup // RGB Level2 Setup
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....... Write( DATA, 0x001E ); Write( COMMAND, 0x0021 ); Write( DATA, 0x0000 ); Write( DATA, 0x0002 ); Write( DATA, 0x0005 ); ....... Write( DATA, 0x001E ); Write( COMMAND, 0x0022 ); Write( DATA, 0x0000 ); Write( DATA, 0x0002 ); Write( DATA, 0x0005 ); ....... Write( DATA, 0x001E ); Write( COMMAND, 0x0023 ); Write( DATA, 0x0000 ); Write( DATA, 0x0002 ); Write( DATA, 0x0005 ); ....... Write( DATA, 0x001E ); Write( COMMAND, 0x0030 ); } ....... // RGB Level15 Setup // Palette FRC2 Setup // RGB Level0 Setup // RGB Level1 Setup // RGB Level2 Setup ....... // RGB Level15 Setup // Palette FRC3 Setup // RGB Level0 Setup // RGB Level1 Setup // RGB Level2 Setup ....... // RGB Level15 Setup // Palette FRC4 Setup // RGB Level0 Setup // RGB Level1 Setup // RGB Level2 Setup ....... // RGB Level15 Setup // Ext = 0
(5) Analog set (ANASET) Command 1; Parameter: 3 (32H) A0 Command Parameter1(P1) Parameter2(P2) Parameter3(P3) Parameter4(P4) 0 1 1 1 1 RD 1 1 1 1 1 WR 0 0 0 0 0 D7 0 * * * * D6 0 * * * * D5 1 * * * * D4 1 * * * * D3 0 * * * * D2 0 P12 * P32 P42 D1 1 P11 P21 P31 P41 D0 0 Function
P10 OSC frequency Adjustment P20 Booster Efficiency Set P30 Bias setting P40 Booster setting
P1: OSC frequency adjustment CL pin frequency ( KHz ) : P12 P10 P10 CL dividing ratio setting = 00H (No division) 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 5.39 5.64 6.18 6.83 7.65 8.68 10.10 12.02 CL pin frequency ( KHz ) : CL dividing ratio setting = 04H (Divided by 2) 2.70 2.82 3.09 3.42 3.82 4.34 5.05 6.01
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OSC frequency can be adjusted by P1 setting and command CAH, see page 46. The default OSC frequency (CL pin frequency) is 5.39 KHz. And the frame frequency is from OSC frequency and duty setting, as the formula shown below: Frame frequency = OSC frequency/(Duty+1) Example: 1. 2. duty=68, P1 setting=[000], frame frequency=5.39KHz/78.12Hz duty=64, P1 setting=[101], frame frequency=8.68KHz/133.53Hz
P2: Booster Efficiency set P21 0 0 1 1 P20 0 1 0 1 Frequency ( Hz ) Level 1 Level 2 Level 3 Level 4
By Booster Stages (2X, 3X, 4X, 5X) and Booster Efficiency (Level1~4) commands, we could easily set the best Booster performance with suitable current consumption. If the Booster Efficiency is set to lower level (level1 is higher than level4). The Boost Efficiency is better than higher level, and it just need few more power consumption current.
P3: Select LCD bias ratio of the voltage required for driving the LCD. P32 0 0 0 0 1 1 1 1 P31 0 0 1 1 0 0 1 1 P30 0 1 0 1 0 1 0 1 LCD bias 1/12 1/11 1/10 1/9 1/8 1/7 1/6 1/5
P4: Booster setting. P42 0 0 0 0 1 P41 0 0 1 1 0 P40 0 1 0 1 0 Booster off 2 times boosting circuit 3 times boosting circuit 4 times boosting circuit 5 times boosting circuit
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(6) Control EEPROM: 1; Parameter: 1 (CDH) A0 Command Parameter1(P1) 0 1 RD 1 1 WR 0 0 D7 1 * D6 1 * D5 0 P15 D4 0 * D3 1 * D2 1 * D1 0 * D0 1 *
P15: when setting "1" P15: when setting "0"
The Write Enable of EEPROM will be opened. The Read Enable of EEPROM will be opened.
(7) Cancel EEPROM Command: 1; Parameter: None (CCH) A0 Command 0 RD 1 RW 0 D7 1 D6 1 D5 0 D4 0 D3 1 D2 1 D1 0 D0 0
(8) Write data to EEPROM (EPMWR) Command: 1; Parameter: None (FCH) A0 Command 0 RD 1 RW 0 D7 1 D6 1 D5 1 D4 1 D3 1 D2 1 D1 0 D0 0
(9) Read data from EEPROM (EPMWR) Command: 1; Parameter: None (FDH) A0 Command 0 RD 1 RW 0 D7 1 D6 1 D5 1 D4 1 D3 1 D2 1 D1 0 D0 1
(10) Display performance adjustment (DISPADJ) Command: 1; Parameter: 1 (FAH) A0 Command Parameter1(P1) 0 1 RD 1 1 WR 0 0 D7 1 * D6 1 * D5 1 * D4 1 P14 D3 1 P13 D2 0 P12 D1 1 P11 D0 0 Function
Display performance adjustment
P10 Fine tuning level set
ST7626 provide the function of 32 levels fine tuning to adjust best crosstalk performance for each module. Just like Vop offset for different modules, the fine tuning level value can also be stored in EEPROM, and therefore each module can have its individual setup for best display performance.
Due to IC and module process variation, it's hard for all modules to have same display performance. By using this command, different modules can adjust to the best performance by having different parameters of DISPADJ. When loading EEPROM, this individual parameter can be loaded into IC and best display performance can be achieved. Detail using method please refer ST7626 EEPROM User Manual guide.
(11) Internal Initialize Preparation (IIPP) Command: 1; Parameter: 1 (F4H) Use this command to set internal initializing for ready status. A0 Command Parameter(P1) 0 1 RD 1 1 RW 0 0 D7 1 0 D6 1 1 D5 1 0 D4 1 1 D3 0 1 D2 1 0 D1 0 0 D0 0 0 Function Internal initialize sequencing
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8.4 EXT="0" or "1" Function Description
(1) Extension instruction disable (EXT IN) Command:1 Parameter: None (30H)
Use the "Ext=0" command table A0 Command 0 RD 1 WR 0 D7 0 D6 0 D5 1 D4 1 D3 0 D2 0 D1 0 D0 0
(2) Extension instruction enable (EXT OUT) Command:1 Parameter: None (31H)
Use the extended command table (EXT="1") A0 Command 0 RD 1 WR 0 D7 0 D6 0 D5 1 D4 1 D3 0 D2 0 D1 0 D0 1
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8.5 Referential Instruction Setup Flow
8.5.1 Initializing with the Built-in Power Supply Circuits
Power On
eeping the /RES Pin = L" ( t > t K " RW ) and waiting for stabilizing the Power
/RES Pin=H" " ait a minute ( t > t R ) W And execute below Instruction Immediately rite Command, 0x31); W( rite Command, 0xF4); W( rite data, 0x58); W(
User Application Setup by Internal Instructions [Sleep Out: 94H] [Internal OSC On: D1H] [Display Control: CAH] [COM Scan Direction: BBH]
User LCD Power Setup by Internal Instructions [Analog Control - LCD Bias Select K : 32H]
[Electronic Volume Control: 81H] [DC-DC Step-up Register Select: 20H] Execute the Load EEPROM Flow Execute the Load Paint Flow ( Adjust for Panel Characteristics )
[Normal / Inverse Display: A6H/A7H] [Data Display Setting: BCH] [Display On: AFH]
[Column Address Setting: 15H] [Page Address Setting: 75H] [Entry Data rite Mode: 5CH] W
End of Initialization
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ExampleG ST7626 Initial setting for 98X68
void ST7626_Init( void ) { Write( COMMAND, 0x30 ); Write( COMMAND, 0x04 ); Write( DATA, 0x3e ); Write( COMMAND, 0x31 ); Write( COMMAND, 0xf4 ); Write( DATA, 0x58 ); Write( COMMAND, 0x30 ); Write( DATA, 0x10 ); Write( DATA, 0x00 ); Write( COMMAND, 0x31 ); Write( COMMAND, 0x32 ); Write( DATA, 0x00 ); Write( DATA, 0x02 ); Write( DATA, 0x03 ); Write( DATA, 0x04 ); Write( COMMAND, 0x30 ); Write( COMMAND, 0x81 ); Write( DATA, 0x2D ); Write( DATA, 0x02 ); Write( COMMAND, 0x20 ); Write( DATA, 0x0b ); delayms(50); LoadEEPROM() LoadPaint(); Write( COMMAND, 0x30 ); Write( COMMAND, 0xa7 ); Write( COMMAND, 0xbb ); Write( DATA, 0x01 ); Write( COMMAND, 0xbc ); Write( DATA, 0x00 ); Write( DATA, 0x00 ); Write( DATA, 0x01 ); Write( COMMAND, 0x75 ); Write( DATA, 0x00 ); Write( DATA, 67 ); Write( COMMAND, 0x15 ); Write( DATA, 0x00 ); Write( DATA, 97 ); Write( COMMAND, 0xaf ); Write( COMMAND, 0x30 ); } // Ext = 0 //Sleep In/Out Preparation //Sleep In/Out Sequencing // Ext = 1 // Internal Initialize Preparation // Internal Initialize Sequencing // Ext = 0 // Duty Setting (= 68) // N-Line Inverse-set value // Ext = 1 // Analog Setting // OSC Freqency adjustment // Booster Efficiency Setting is level3 // Bias Setting (=1/9) // Booster is X5 // Ext = 0 // Electronic Volume Control // EV:Vop[5:0]_6bit // EV:Vop[8:6]_3bit // Vop is 10.52V under this condition for example // Power Control // B/F/R = On/On/On // Delay 50ms // Load EEPROM example program (refer page 68) // Load Gamma Table Parameter (refer page 61) // Ext = 0 // Inverse Display // Com Scan Direction // 0~33 / 67~34 // Data Scan Direction // Page / Column Address Setting // RGB arrangement (0:RGB 1:BGR) // Gray-scale setup ( 64-gray: 01H) // Page address set // From page address 0 // to page address 67 // Column address set // From column address 0 // to column address 97 // Display On // Ext = 0
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ExampleG Load EEPROM
void LoadEEPROM( void ) { Write( COMMAND, 0x31 ); Write( COMMAND, 0xcd ); Write( DATA, 0x00 ); delayms(50); Write( COMMAND, 0xfd ); delayms(50); Write( COMMAND, 0xcc ); Write( COMMAND, 0x30 ); } // Ext = 1 // Enable EEPROM // // Delay 50ms // Load EEPROM // Delay 50ms // Disable EEPROM // Ext = 0
8.5.2 Data Displaying
Normal State
Display Data RAM Addressing by Instruction [Data Control: BCH] [Set Page Address: 75H] [Set Column Address: 15H] [Entry Memory rite Mode: 5CH] W
Display Data Write [Display Data Write]
No
End of Display Data Write ?
Yes
End of Data Display
Figure 8.5.2.1 Data Displaying
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ExampleG Display for 98X68
void Display( char *pattern ) { unsigned char i, j; Write( COMMAND, 0x30 ); Write( COMMAND, 0x15 ); Write( DATA, 0 ); Write( DATA, 97 ); Write( COMMAND, 0x75 ); Write( DATA, 0 ); Write( DATA, 67 ); Write( COMMAND, 0x5c ) for( j = 0; j < 68 ; j++ ) for( i = 0 ; i < 98 ; i++ ) Write( DATA, pattern[ j ][ i ] ); } // Ext = 0 // Column address set // From column address 0 to 97 // Page address set // From page address 0 to 67 // Entry Memory Write Mode
// Display Data Write
8.5.3 Partial Display In/Out
Figure 8.5.3.1 Partial Display In/Out
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ExampleG Partial Display In Operation
void PartailIn( unsigned char start_block, unsigned char end_blo { Write( COMMAND, 0x30 ); Write( COMMAND, 0xA8); Write( DATA, start_block ); Write( DATA, end_block ); } void PartailOut( void ) { Write( COMMAND, 0x30 ); Write( COMMAND, 0xA9 ); } void main() { PartialIn( 11, 18 ); Windowing( 0, 11*4, 131, 18*4 ); PartialDisplay( display_pattern ); . . . PartialOut(); } // entry partial display mode // set the page and column range // Fill the data into partial display area // Ext = 0 // Partial Display In Function // Start Block // End Block ck )
// Ext = 0 // Partial Display Out Function
// Out of partial display mode
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8.5.4 Scroll Display
Figure 8.5.4.1 Scroll Display
ExampleG Screen Scroll Operation
void CenterScreenScroll( void ) { Write( COMMAND, 0x30 ); Write( COMMAND, 0xAA); Write( DATA, 0x0a ); Write( DATA, 0x14 ); Write( DATA, 0x14 ); Write( DATA, 0x00 ); ScrollUp() or ScrollDown(); } void TopScreenScroll( void ) { Write( COMMAND, 0x30 ); Write( COMMAND, 0xAA); Write( DATA, 0x00 ); Write( DATA, 0x14 ); Write( DATA, 0x14 ); Write( DATA, 0x01 ); ScrollUp() or ScrollDown(); } // Ext = 0 // Partial Display In Function // Top_Block=10 // Bottom_Block=20 // Number of Specified Blocks=Bottom_Block=20 // Area Scroll Type=Center Screen Scroll // Scroll Up or Scroll Down
// Ext = 0 // Partial Display In Function // Top_Block=0 // Bottom_Block=20 // Number of Specified Blocks=Bottom_Block=20 // Area Scroll Type=Top Screen Scroll // Scroll Up or Scroll Down
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void BottomScreenScroll( void ) { Write( COMMAND, 0x30 ); Write( COMMAND, 0xAA); Write( DATA, 0x0a ); Write( DATA, 0x20 ); Write( DATA, 0x20 ); Write( DATA, 0x02 ); ScrollUp() or ScrollDown(); } void WholeScreenScroll( void ) { Write( COMMAND, 0x30 ); Write( COMMAND, 0xAA); Write( DATA, 0x00 ); Write( DATA, 0x20 ); Write( DATA, 0x20 ); Write( DATA, 0x03 ); ScrollUp() or ScrollDown(); } void ScrollUp( void ) { Write( COMMAND, 0x30 ); Write( COMMAND, 0xAB); Write( DATA, Top_Block); Delay(); Write( COMMAND, 0x00AB); Write( DATA, Top_Block +1 ); Delay(); Write( COMMAND, 0x00AB); Write( DATA, Top_Block +2 ); Delay(); ...... ...... Write( COMMAND, 0x00AB); Write( DATA, Bottom_Block ); Delay(); } void ScrollDown( void ) { Write( COMMAND, 0x30 ); Write( COMMAND, 0x00AB); Write( DATA, Bottom_Block); Delay(); Write( COMMAND, 0x00AB); Write( DATA, Bottom_Block -1 ); Delay(); Write( COMMAND, 0x00AB); Write( DATA, Bottom_Block -2 ); Delay(); ...... ...... Write( COMMAND, 0x00AB); Write( DATA, Top _Block ); Delay(); } // Ext = 0 // Partial Display In Function // Top_Block=10 // Bottom_Block=32 // Number of Specified Blocks=Bottom_Block=32 // Area Scroll Type=Bottom Screen Scroll // Scroll Up or Scroll Down
// Ext = 0 // Partial Display In Function // Top_Block=0 // Bottom_Block=32 // Number of Specified Blocks=Bottom_Block=32 // Area Scroll Type=Whole Screen Scroll // Scroll Up or Scroll Down
// Ext = 0 // Scroll Start Set // Start Block Address=Top_Block // Delay // Scroll Start Set // Start Block Address= Top_Block+1 // Delay // Scroll Start Set // Start Block Address= Top_Block +2 // Delay // Scroll Start Set // Start Block Address= Bottom_Block // Delay
// Ext = 0 // Scroll Start Set // Start Block Address= Bottom_Block // Delay // Scroll Start Set // Start Block Address= Bottom_Block -1 // Delay // Scroll Start Set // Start Block Address= Bottom_Block -2 // Delay // Scroll Start Set // Start Block Address= Top_Block // Delay
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8.5.5 Read-Modify-Write Cycle
Figure 8.5.5.1 Read-Write-Modify Cycle
ExampleG Read-Write-Modify Cycle
void ReadModifyWriteIn( void ) { Write( COMMAND, 0x30 ); Write( COMMAND, 0xE0 ); } void ReadModifyWriteOut( void ) { Write( COMMAND, 0x30 ); Write( COMMAND, 0xEE ); } // Ext = 0 // Entry the Read-Modify-Write mode
// Ext = 0 // Out of partial display mode
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extern unsigned char *display_pattern; void main() { unsigned pixel, i; Windowing( 11, 31, 80, 50 ); ReadModifyWriteIn(); for( i = 0 ; i < 1400 ; i++ ) { Read( DATA ); pixel = Read( DATA ); pixel = pixel & 0x07ff; Write( DATA, pixel ); } ReadModifyWriteOut(); } // set the page and column range // entry the Read-Modify-Write mode
// For dummy read // Pixel read // Pixel modify: red filter
// Out of Read-Modify-Write mode
8.5.6 Power OFF
Power OFF
Normal State
Execute the Sleep In Flow
Keeping /RES Pin =L
Power Off (VDD-VSS)
End of Power OFF
VDD
/RES
tR Internal State Normal State Reset
tR >
Power Off
12 ms
Keep the /RES = Low
Figure 8.5.6.1 Power off
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8.5.7 Sleep In/Out
Normal State Sleep In Status
Start of Sleep In Sleep In Sequencing : [Display Off: AEH] [Booster Off Only: 20H^03H] [Set Sleep In Preparation: 04H^3FH] Delay 500ms [Set Sleep In by Instruction: 95H] End of Sleep In
Start of Sleep Out
Sleep Out Sequencing : [Set Sleep Out Preparation: 04H^3EH] [Set Analog Power Control: 20H^0BH]
[Set Sleep Out by Instruction: 94H] Delay 100ms [Display On: AFH] End of Sleep Out
Fig 8.5.7.1 Sleep In/Out Flow
ExampleG Sleep In Operation
void SleepIn( void ) { Write( COMMAND, 0x30 ); Write( COMMAND, 0xae ); Write( COMMAND, 0x20); Write( DATA, 0x03 ); Write( COMMAND, 0x04 ); Write( DATA, 0x3f ); Delay( 500ms); Write( COMMAND, 0x95 ); } // Ext = 0 // Display Off // Power Control // B/F/R = Off/On/On // Sleep In Preparation // Sleep In Sequencing // Delay 500ms // Sleep In
ExampleG Sleep Out Operation
void SleepOut( void ) { Write( COMMAND, 0x30 ); Write( COMMAND, 0x04 ); Write( DATA, 0x3e ); Write( COMMAND, 0x20 ); Write( DATA, 0x0b ); Write( COMMAND, 0x94 ); Delay( 100ms ); Write( COMMAND, 0xaf ); } // Ext = 0 // Sleep Out Preparation // Sleep Out Sequencing // Power Control // B/F/R = On/On/On // Sleep Out // Delay 100ms // Display On
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9. LIMITING VALUES
In accordance with the Absolute Maximum Rating System of Bare Die; see notes 1 and 2. Parameter Power supply voltage Power supply voltage Power supply voltage Input voltage Output voltage Operating temperature (die) Storage temperature (die) Symbol VDD, VDD1~VDD5 VLCDIN V1, V2, V3, V4 VIN VO TOPR TSTR Conditions -0.5 ~ +4.0 -0.5 ~ +20 0.3 to VLCDIN -0.5 to VDD+0.5 -0.5 to VDD+0.5 -30 to +85 -40 to +125 Unit V V V V V C C
VLCD
V1 to V4
VDD
VDD
VSS System (MPU) side
VSS ST7626chip side
VSS
Notes 1. Stresses above those listed under Limiting Values may cause permanent damage to the device. 2. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. 3. Insure that the voltage levels of V1, V2, V3, and V4 are always such that VLCDIN V0 U V1U V2 U V3 V4 VSS U U U
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10. HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling MOS devices (see "Handling MOS devices").
11. DC CHARACTERISTICS
VDD = 1.8 V to 3.3V; VSS = 0 V; V0 = 3.76 to 18.0V; Tamb = -30J to +85J ; unless otherwise specified. Item High-level Input Voltage Low-level Input Voltage High-level Output Voltage Low-level Output Voltage Input leakage current Output leakage current Liquid Crystal Driver ON Resistance Internal Oscillator External Input Oscillator Frequency Frame frequency fFRAME Symbol VIHC VILC VOHC VOLC ILI ILO VIN = VDD or VSS VIN = VDD or VSS Ta = 25C V0IN = 15.0 RON (Relative To VSS) fOSC fCL 1/68 duty V V0IN = 8.0 V Condition Rating Min. 0.7 x VDD VSS 0.7 x VDD VSS -1.0 -3.0 -- -- -- -- Typ. -- -- -- -- -- -- 1 1.3 5.39 167.09 Max. VDD 0.3 x VDD VDD 0.3 x VDD 1.0 3.0 -- -- 12.02 372.62 kHz kHz *6 OSC Units V V V V A A Applicable Pin *1 *1 *2 *2 *3 *4 SEGn COMn *5
K
Ta = 25C Internal OSC: 31 PWM fFRAME = fOSC /(Duty+1) External OSC: fFRAME = fCL /[31*(Duty+1)] Hz
Item
Symbol VDD VDD1 VDD2
Condition
Rating Min. 1.7 Typ. -- Max. 3.4
Units
Applicable Pin
Operating Voltage (1)
(Relative to VSS)
V
VSS*7
Internal Power
Operating Voltage (2)
VDD3 VDD4 VDD5
(Relative to VSS)
2.4
--
3.4
V
VSS
Supply Step-up output voltage Circuit Voltage regulator Circuit Operating Voltage
VLCDOUT
(Relative To VSS)
--
--
20
V
VLCDOUT
VLCDIN
(Relative To VSS)
--
--
20
V
VLCDIN
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Dynamic Consumption Current : During Display, with the Internal Power Supply OFF Current consumed by total ICs when an external power supply is used . Test pattern Display Pattern Normal(Bare die) Power Down (Bare die) Symbol Condition Bare Die, VDD = 2.8 V, Booster x 5 @ 1/9 bias,1/68 duty,Vop=11V Ta = 25C Rating Min. -- Typ. 350 Max. -- Units Notes
ISS
A
*8
ISS
--
--
10
A
Notes to the DC characteristics 1. The maximum possible VLCD voltage that may be generated is dependent on voltage, temperature and (display) load Internal clock. 2. Power-down mode. During power down all static currents are switched off. 3. If external VLCD, the display load current is not transmitted to IDD. 4. VLCD external voltage applied to VLCDIN pin; VLCDIN disconnected from VLCDOUT
References for items market with *
*1 The A0, D0 to D5, D6, D7, SI, SCL, E_RD, RW_WR, /CS, RST terminals. *2 The D0 to D7. *3 The A0, E_RD, RW_WR, /CS, RST terminals. *4 Applies when the D0 to D5, D6, D7, SI, SCL, terminals are in a high impedance state. *5 These are the resistance values for when a 0.2 x V0 voltage is applied between the output terminal SEGn or COMn and the various power supply terminals (V1, V2, V3, and V4). These are specified for the operating voltage range. RON = (0.2 V0 )/ I (Where I is the current that flows when 0.2 V0 is applied while the power supply is ON.) *6 The relationship between the oscillator frequency and the frame rate frequency under CL dividing ratio setting = 00H. *7 While a broad range of operating voltages is guaranteed, performance cannot be guaranteed if there are sudden fluctuations to the voltage while the MPU is being accessed. *8 It indicates the current consumed on ICs alone when the internal oscillator circuit and display are turned on.
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12. TIMING CHARACTERISTICS
System Bus Read/Write Characteristics 1 (For the 8080 Series MPU)
A0 tAW8 /CS tCYC8 tCCLR,tCCLW /WR,/RD tCCHR,tCCHW tDS8 D0 to D7 (Write) tACC8 D0 to D7 (Read) tOH8 tDH8 tAH8
tAS8
Figure 12.1
(VDD=3.3V,Ta= -30 to 85C) Item Address hold time Address setup time Address setup time System cycle time (WRITE) /WR L pulse width (WRITE) /WR H pulse width (WRITE) System cycle time (READ) /RD L pulse width (READ) /RD H pulse width (READ) WRITE data setup time WRITE data hold time READ access time READ Output disable time D0 to D7 RD WR A0 Signal Symbol tAH8 tAS8 tAW8 tCYC8 tCCLW tCCHW tCYC8 tCCLR tCCHR tDS8 tDH8 tACC8 tOH8 CL = 100 pF CL = 100 pF Condition Rating Min. 10 60 0 180 60 120 200 80 120 60 10 -- -- Max. -- -- -- -- -- -- -- -- -- -- -- 70 60 ns Units
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(VDD=2.8V,Ta= -30 to 85C) Item Address hold time Address setup time Address setup time System cycle time (WRITE) /WR L pulse width (WRITE) /WR H pulse width (WRITE) System cycle time (READ) /RD L pulse width (READ) /RD H pulse width (READ) WRITE data setup time WRITE data hold time READ access time READ Output disable time D0 to D7 RD WR A0 Signal Symbol tAH8 tAS8 tAW8 tCYC8 tCCLW tCCHW tCYC8 tCCLR tCCHR tDS8 tDH8 tACC8 tOH8 CL = 100 pF CL = 100 pF Condition Rating Min. 10 80 0 220 80 140 280 100 180 80 10 -- -- Max. -- -- -- -- -- -- -- -- -- -- -- 75 65 ns Units
(VDD=1.8V,Ta= -30 to 85C ) Item Address hold time Address setup time Address setup time System cycle time (WRITE) /WR L pulse width (WRITE) /WR H pulse width (WRITE) System cycle time (READ) /RD L pulse width (READ) /RD H pulse width (READ) WRITE data setup time WRITE data hold time READ access time READ Output disable time D0 to D7 RD WR A0 Signal Symbol tAH8 tAS8 tAW8 tCYC8 tCCLW tCCHW tCYC8 tCCLR tCCHR tDS8 tDH8 tACC8 tOH8 CL = 100 pF CL = 100 pF Condition Rating Min. 10 180 30 430 150 280 450 190 230 150 10 -- -- Max. -- -- -- -- -- -- -- -- -- -- -- 100 80 ns Units
*1 The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. When the system cycle time is extremely fast, (tr +tf) O (tCYC8 - tCCLW - tCCHW) for (tr + tf) O (tCYC8 - tCCLR - tCCHR) are specified.
*2 All timing is specified using 20% and 80% of VDD as the reference. *3 tCCLW and tCCLR are specified as the overlap between /CS being "L" and WR and RD being at the "L" level.
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System Bus Read/Write Characteristics 1 (For the 6800 Series MPU)
A0 R/W tAW6 /CS1 tCYC6 tCCLR,tCCLW E tCCHR,tCCHW tDS6 D0 to D7 (Write) tACC6 D0 to D7 (Read)
Figure 12.2
tAS6
tAH6
tDH6
tOH6
(VDD=3.3V,Ta= -30 to 85C ) Item Address hold time Address setup time Address setup time System cycle time (WRITE) Enable L pulse width (WRITE) Enable H pulse width (WRITE) System cycle time (READ) Enable L pulse width (READ) Enable H pulse width (READ) WRITE data setup time WRITE data hold time READ access time READ Output disable time D0 to D7 RD WR A0 Signal Symbol tAH6 tAS6 tAW6 tCYC6 tCCLW tCCHW tCYC6 tCCLR tCCHR tDS6 tDH6 tACC6 tOH6 CL = 100 pF CL = 100 pF Condition Rating Min. 10 60 0 180 120 60 200 120 80 60 10 -- -- Max. -- -- -- -- -- -- -- -- -- -- -- 70 60 ns Units
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(VDD=2.8V,Ta= -30 to 85C ) Item Address hold time Address setup time Address setup time System cycle time (WRITE) Enable L pulse width (WRITE) Enable H pulse width (WRITE) System cycle time (READ) Enable L pulse width (READ) Enable H pulse width (READ) WRITE data setup time WRITE data hold time READ access time READ Output disable time D0 to D7 RD WR A0 Signal Symbol tAH6 tAS6 tAW6 tCYC6 tCCLW tCCHW tCYC6 tCCLR tCCHR tDS6 tDH6 tACC6 tOH6 CL = 100 pF CL = 100 pF Condition Rating Min. 10 80 0 220 140 80 220 120 100 80 10 -- -- Max. -- -- -- -- -- -- -- -- -- -- -- 75 65 ns Units
(VDD=1.8V,Ta= -30 to 85C ) Item Address hold time Address setup time Address setup time System cycle time (WRITE) Enable L pulse width (WRITE) Enable H pulse width (WRITE) System cycle time (READ) Enable L pulse width (READ) Enable H pulse width (READ) WRITE data setup time WRITE data hold time READ access time READ Output disable time D0 to D7 RD WR A0 Signal Symbol tAH6 tAS6 tAW6 tCYC6 tCCLW tCCHW tCYC6 tCCLR tCCHR tDS6 tDH6 tACC6 tOH6 CL = 100 pF CL = 100 pF Condition Rating Min. 10 180 30 430 280 150 400 220 180 150 10 -- -- Max. -- -- -- -- -- -- -- -- -- -- -- 100 80 ns Units
*1 The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. When the system cycle time is extremely fast, (tr +tf) O (tCYC6 - tEWLW - tEWHW) for (tr + tf) O (tCYC6 - tEWLR - tEWHR) are specified.
*2 All timing is specified using 20% and 80% of VDD as the reference. *3 tEWLW and tEWLR are specified as the overlap between /CS being "L" and E.
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Serial Interface Characteristics (For 4-Line Interface)
tCSS /CS1 tSAS A0 tSCYC SCL tf tSDS SI tSLW tSHW tr tSDH tSAH tCSH
Fig 12.3
(VDD=3.3V,Ta= -30 to 85C ) Item Serial clock period SCL "H" pulse width SCL "L" pulse width Address setup time Address hold time Data setup time Data hold time CS-SCL setup time CS-SCL hold time A0 SCL Signal Symbol tSCYC tSHW tSLW tSAS tSAH tSDS tSDH tCSS tCSH Condition Rating Min. 80 40 40 10 10 10 30 20 30 Max. -- -- -- -- -- -- -- -- -- ns Units
SI
/CS
(VDD=2.8V,Ta= -30 to 85C ) Item Serial clock period SCL "H" pulse width SCL "L" pulse width Address setup time Address hold time Data setup time Data hold time CS-SCL setup time CS-SCL hold time A0 SCL Signal Symbol tSCYC tSHW tSLW tSAS tSAH tSDS tSDH tCSS tCSH Condition Rating Min. 100 50 50 10 10 10 30 20 40 Max. -- -- -- -- -- -- -- -- -- ns Units
SI
/CS
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(VDD=1.8V,Ta= -30 to 85C ) Item Serial clock period SCL "H" pulse width SCL "L" pulse width Address setup time Address hold time Data setup time Data hold time CS-SCL time CS-SCL time A0 SCL Signal Symbol tSCYC tSHW tSLW tSAS tSAH tSDS tSDH tCSS tCSH Condition Rating Min. 180 90 90 10 50 10 45 10 80 Max. -- -- -- -- -- -- -- -- -- ns Units
SI
/CS
*1 The input signal rise and fall time (tr, tf) are specified at 15 ns or less. *2 All timing is specified using 20% and 80% of VDD as the standard.
Serial Interface Characteristics (For 3-Line Interface)
tCSS /CS1 tCSH
tSCYC SCL tf tSDS SI tSLW tSHW tr tSDH
Fig 12.4
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(VDD=3.3V,Ta= -30 to 85C ) Item Serial clock period SCL "H" pulse width SCL "L" pulse width Data setup time Data hold time CS-SCL setup time CS-SCL hold time SI SCL Signal Symbol tSCYC tSHW tSLW tSDS tSDH tCSS tCSH Condition Rating Min. 80 40 40 10 30 20 50 Max. -- -- -- -- -- -- -- ns Units
/CS
(VDD=2.8V,Ta= -30 to 85C ) Item Serial clock period SCL "H" pulse width SCL "L" pulse width Data setup time Data hold time CS-SCL time CS-SCL time SI SCL Signal Symbol tSCYC tSHW tSLW tSDS tSDH tCSS tCSH Condition Rating Min. 100 50 50 10 30 20 50 Max. -- -- -- -- -- -- -- ns Units
/CS
(VDD=1.8V,Ta= -30 to 85C ) Item Serial clock period SCL "H" pulse width SCL "L" pulse width Data setup time Data hold time CS-SCL time CS-SCL time SI SCL Signal Symbol tSCYC tSHW tSLW tSDS tSDH tCSS tCSH Condition Rating Min. 180 90 90 10 45 10 80 Max. -- -- -- -- -- -- -- ns Units
/CS
*1 The input signal rise and fall time (tr, tf) are specified at 15 ns or less. *2 All timing is specified using 20% and 80% of VDD as the standard.
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13. RESET TIMING
/RES tRW
tR Internal status During reset
Fig 13.1
Reset complete
(VDD = 3.3V , Ta = -30 to 85C ) Item Reset time Reset "L" pulse width RESB Signal Symbol tR tRW Condition Rating Min. -- 1.2 Typ. -- -- Max. 1 -- Units us us
(VDD = 2.8V , Ta = -30 to 85C ) Item Reset time Reset "L" pulse width RESB Signal Symbol tR tRW Condition Rating Min. -- 1.5 Typ. -- -- Max. 1.5 -- Units us us
(VDD = 1.8V , Ta = -30 to 85C ) Item Reset time Reset "L" pulse width RESB Signal Symbol tR tRW Condition Rating Min. -- 2 Typ. -- -- Max. 2 -- Units us us
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14. THE MPU INTERFACE (REFERENCE EXAMPLES)
The ST7626 Series can be connected to either 8080 Series MPUs or to 6800 Series MPUs. Moreover, using the serial interface it is possible to operate the ST7626 series chips with fewer signal lines. The display area can be enlarged by using multiple ST7626 Series chips. When this is done, the chip select signal can be used to select the individual Ics to access. (1) 8080 Series MPUs
VDD VCC A0 CS1 MPU DO to D7 RD WR RES RESET A0 CS1 D0 to D7 /RD (E) /WR (R/W) /RES VSS VDD IF1 IF2 IF3 ST7626
GND
VSS
(2) 6800 Series MPUs
VDD VCC A0 CS1 MPU DO to D7 RD WR RES RESET A0 CS1 D0 to D7 E(/RD) R/W (/W R) /RES VSS VDD IF1 IF2 IF3 ST7626
GND
VSS
(3) Using the Serial Interface (4-line interface)
VDD VDD A0 CS1 MPU A0 CS1 IF1 IF2 IF3 ST7626 VSS VSS
VCC
Port 1 Port 2 RES GND RESET
SI SCL /RES
Ver 1.5
87/94
2007/01/20
ST7626
(4) Using the Serial Interface (3-line interface)
VDD or VSS VCC VDD IF1 IF2 IF3
CS1 MPU
CS1
Port 1 Port 2 RES GND RESET
SI SCL /RES VSS
ST7626
VSS
Ver 1.5
88/94
2007/01/20
ST7626
Application Circuits ( A ) 80 Series 16-bit Parallel Interface:
Interface : 8080series-16bits VDD1(VDD,VDD1)=1.8~3.3V VDD2(VDD2~VDD5)=2.4~3.3V CSEL=H (Interlace Mode) IF1=H;IF2=H;IF3=H C0: 1.0~2.2uF/25V
Ver 1.5
89/94
2007/01/20
ST7626
( B ) 80 Series 8-bit Parallel Interface:
Interface : 8080series-8bits VDD1(VDD,VDD1)=1.8~3.3V VDD2(VDD2~VDD5)=2.4~3.3V CSEL=H (Interlace Mode) IF1=H;IF2=H;IF3=L C0: 1.0~2.2uF/25V
Ver 1.5 90/94 2007/01/20
ST7626
( C ) 3 Line Serial Peripheral Interface:
Interface : 9-bit Serial(3-Line) VDD1(VDD,VDD1)=1.8~3.3V VDD2(VDD2~VDD5)=2.4~3.3V CSEL=H (Interlace Mode) IF1=L;IF2=L;IF3=H C0: 1.0~2.2uF/25V
Ver 1.5
91/94
2007/01/20
ST7626
( D ) 4 Line Serial Peripheral Interface:
Interface : 8-bit Serial(4-Line) VDD1(VDD,VDD1)=1.8~3.3V VDD2(VDD2~VDD5)=2.4~3.3V CSEL=H (Interlace Mode) IF1=L;IF2=L;IF3=L C0: 1.0~2.2uF/25V
Ver 1.5 92/94 2007/01/20
ST7626
16. Application Note of VLCD and Vop (V0) ITO Layout
When using internal voltage generator, VLCDIN VLCDOUT must be connected together. V0IN B and V0OUT must be connected together too. In the following is the ITO layout for VLCDINB VLCDOUTB V0IN and V0OUT individually. Please follow the way as below for these two LCD power voltages.
NOTE: Microprocessor interfece pins should not be floating in any operation mode.
Ver 1.5
93/94
2007/01/20
ST7626
ST7626 Serial Specification Revision History
Version 0.x 1.0 1.1 1.2 1.3 1.4 1.5 Date -Preliminary version Description
2006/04/10 First issue. 2006/5/23 2006/7/23 Change the limitation voltage (P77): VDD, VDD1=1.7V~3.4V VDD2,VDD3, VDD4, VDD5=2.4V~3.4V
Change write EEPROM example program ( P.43) Add microprossoer notice item (P.13,P93) Add Vref Pin notice item (P.14,P11) 2006/09/25 Modifty Application circuit vref Pin section (P89, P90,P91,P92 )
2006/10/31 Modifty page 67: ST7626 initial code example program 2007/01/20 Modifty page application circuit : page 89~page 93
Ver 1.5
94/94
2007/01/20

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